CVD-grown back-gated MoS2transistors

Carlos Marquez; Norberto Salazar; Farzan Gity; Carlos Navarro; Gioele Mirabelli; Ray Duffy; Jose Galdon; Santiago Navarro; Paul K. Hurley; Francisco Gamiz

doi:10.1109/EUROSOI-ULIS49407.2020.9365295

CVD-grown back-gated MoS₂transistors

Carlos Marquez
, Norberto Salazar
, Farzan Gity
, Carlos Navarro
, Gioele Mirabelli
, Ray Duffy
, Jose Galdon
, Santiago Navarro
, Paul K. Hurley
, Francisco Gamiz

University of Granada

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

In this work, the electrical performance and reliability of scalable CVD-grown MoS2 transistors have been evaluated. Transfer and output characteristics, hysteresis and low-frequency noise signature have been characterized revealing the influence of surface and oxide interfaces and the disturbance due to number of carrier fluctuations on the back-gated transistor response.

Original language	English
Title of host publication	2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728187655
DOIs	https://doi.org/10.1109/EUROSOI-ULIS49407.2020.9365295
Publication status	Published - 1 Sep 2020
Event	2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020 - Caen, France Duration: 1 Sep 2020 → 30 Sep 2020

Publication series

Name	2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020

Conference

Conference	2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020
Country/Territory	France
City	Caen
Period	1/09/20 → 30/09/20

Access to Document

10.1109/EUROSOI-ULIS49407.2020.9365295

Cite this

Marquez, C., Salazar, N., Gity, F., Navarro, C., Mirabelli, G., Duffy, R., Galdon, J., Navarro, S., Hurley, P. K., & Gamiz, F. (2020). CVD-grown back-gated MoS₂transistors. In 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020 Article 9365295 (2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EUROSOI-ULIS49407.2020.9365295

Marquez, Carlos ; Salazar, Norberto ; Gity, Farzan et al. / CVD-grown back-gated MoS₂transistors. 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020. Institute of Electrical and Electronics Engineers Inc., 2020. (2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020).

@inproceedings{61d5801a4565430b950c8995220e2c14,

title = "CVD-grown back-gated MoS2transistors",

abstract = "In this work, the electrical performance and reliability of scalable CVD-grown MoS2 transistors have been evaluated. Transfer and output characteristics, hysteresis and low-frequency noise signature have been characterized revealing the influence of surface and oxide interfaces and the disturbance due to number of carrier fluctuations on the back-gated transistor response.",

author = "Carlos Marquez and Norberto Salazar and Farzan Gity and Carlos Navarro and Gioele Mirabelli and Ray Duffy and Jose Galdon and Santiago Navarro and Hurley, \{Paul K.\} and Francisco Gamiz",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020 ; Conference date: 01-09-2020 Through 30-09-2020",

year = "2020",

month = sep,

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doi = "10.1109/EUROSOI-ULIS49407.2020.9365295",

language = "English",

series = "2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Marquez, C, Salazar, N, Gity, F, Navarro, C, Mirabelli, G, Duffy, R, Galdon, J, Navarro, S, Hurley, PK & Gamiz, F 2020, CVD-grown back-gated MoS₂transistors. in 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020., 9365295, 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020, Institute of Electrical and Electronics Engineers Inc., 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020, Caen, France, 1/09/20. https://doi.org/10.1109/EUROSOI-ULIS49407.2020.9365295

CVD-grown back-gated MoS₂transistors. / Marquez, Carlos; Salazar, Norberto; Gity, Farzan et al.
2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9365295 (2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

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Marquez C, Salazar N, Gity F, Navarro C, Mirabelli G, Duffy R et al. CVD-grown back-gated MoS₂transistors. In 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9365295. (2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020). doi: 10.1109/EUROSOI-ULIS49407.2020.9365295