Delay dependent power optimisation of combinational circuits using AND-Inverter graphs

Rashmi Mehrotra; Tom English; Emanuel Popovici; Michel Schellekens

doi:10.1109/SOCC.2010.5784661

Delay dependent power optimisation of combinational circuits using AND-Inverter graphs

Rashmi Mehrotra
, Tom English
, Emanuel Popovici
, Michel Schellekens

University College Cork

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

Dynamic power dissipation due to switching activity has been one of the major concerns in power optimisation. By approximating the switching activity of circuit nodes as internal switching probabilities using AND Inverter graphs (AIGs), it is possible to estimate and optimise power dissipation. In our work, the internal switching probabilities are derived via probabilistic estimation method under a variable delay model. Local reordering delay dependent rules are applied on the AIG nodes for the minimisation of overall sum of switching probability. Optimisation techniques such as simulated annealing for conversions from higher switching probability network to lower switching probability network are used in this paper. Combinational circuits used in our work are up to 100k gates and they are implemented using ROM.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2010
Pages	9-14
Number of pages	6
DOIs	https://doi.org/10.1109/SOCC.2010.5784661
Publication status	Published - 2010
Event	23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States Duration: 27 Sep 2010 → 29 Sep 2010

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference	23rd IEEE International SOC Conference, SOCC 2010
Country/Territory	United States
City	Las Vegas, NV
Period	27/09/10 → 29/09/10

Access to Document

10.1109/SOCC.2010.5784661

Cite this

@inbook{3ffb995de0c7443b8c6fd46cafaa3b0c,

title = "Delay dependent power optimisation of combinational circuits using AND-Inverter graphs",

abstract = "Dynamic power dissipation due to switching activity has been one of the major concerns in power optimisation. By approximating the switching activity of circuit nodes as internal switching probabilities using AND Inverter graphs (AIGs), it is possible to estimate and optimise power dissipation. In our work, the internal switching probabilities are derived via probabilistic estimation method under a variable delay model. Local reordering delay dependent rules are applied on the AIG nodes for the minimisation of overall sum of switching probability. Optimisation techniques such as simulated annealing for conversions from higher switching probability network to lower switching probability network are used in this paper. Combinational circuits used in our work are up to 100k gates and they are implemented using ROM.",

author = "Rashmi Mehrotra and Tom English and Emanuel Popovici and Michel Schellekens",

year = "2010",

doi = "10.1109/SOCC.2010.5784661",

language = "English",

isbn = "9781424466832",

series = "Proceedings - IEEE International SOC Conference, SOCC 2010",

pages = "9--14",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2010",

note = "23rd IEEE International SOC Conference, SOCC 2010 ; Conference date: 27-09-2010 Through 29-09-2010",

}

Mehrotra, R, English, T, Popovici, E & Schellekens, M 2010, Delay dependent power optimisation of combinational circuits using AND-Inverter graphs. in Proceedings - IEEE International SOC Conference, SOCC 2010., 5784661, Proceedings - IEEE International SOC Conference, SOCC 2010, pp. 9-14, 23rd IEEE International SOC Conference, SOCC 2010, Las Vegas, NV, United States, 27/09/10. https://doi.org/10.1109/SOCC.2010.5784661

Delay dependent power optimisation of combinational circuits using AND-Inverter graphs. / Mehrotra, Rashmi; English, Tom; Popovici, Emanuel et al.
Proceedings - IEEE International SOC Conference, SOCC 2010. 2010. p. 9-14 5784661 (Proceedings - IEEE International SOC Conference, SOCC 2010).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - Delay dependent power optimisation of combinational circuits using AND-Inverter graphs

AU - Mehrotra, Rashmi

AU - English, Tom

AU - Popovici, Emanuel

AU - Schellekens, Michel

PY - 2010

Y1 - 2010

N2 - Dynamic power dissipation due to switching activity has been one of the major concerns in power optimisation. By approximating the switching activity of circuit nodes as internal switching probabilities using AND Inverter graphs (AIGs), it is possible to estimate and optimise power dissipation. In our work, the internal switching probabilities are derived via probabilistic estimation method under a variable delay model. Local reordering delay dependent rules are applied on the AIG nodes for the minimisation of overall sum of switching probability. Optimisation techniques such as simulated annealing for conversions from higher switching probability network to lower switching probability network are used in this paper. Combinational circuits used in our work are up to 100k gates and they are implemented using ROM.

AB - Dynamic power dissipation due to switching activity has been one of the major concerns in power optimisation. By approximating the switching activity of circuit nodes as internal switching probabilities using AND Inverter graphs (AIGs), it is possible to estimate and optimise power dissipation. In our work, the internal switching probabilities are derived via probabilistic estimation method under a variable delay model. Local reordering delay dependent rules are applied on the AIG nodes for the minimisation of overall sum of switching probability. Optimisation techniques such as simulated annealing for conversions from higher switching probability network to lower switching probability network are used in this paper. Combinational circuits used in our work are up to 100k gates and they are implemented using ROM.

UR - https://www.scopus.com/pages/publications/79960718213

U2 - 10.1109/SOCC.2010.5784661

DO - 10.1109/SOCC.2010.5784661

M3 - Chapter

AN - SCOPUS:79960718213

SN - 9781424466832

T3 - Proceedings - IEEE International SOC Conference, SOCC 2010

SP - 9

EP - 14

BT - Proceedings - IEEE International SOC Conference, SOCC 2010

T2 - 23rd IEEE International SOC Conference, SOCC 2010

Y2 - 27 September 2010 through 29 September 2010

ER -

Delay dependent power optimisation of combinational circuits using AND-Inverter graphs

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this