Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole

  • J. Franco
  • , A. Vais
  • , S. Sioncke
  • , V. Putcha
  • , B. Kaczer
  • , B. S. Shie
  • , X. Shi
  • , R. Mahlouji
  • , L. Nyns
  • , D. Zhou
  • , N. Waldron
  • , J. W. Maes
  • , Q. Xie
  • , M. Givens
  • , F. Tang
  • , X. Jiang
  • , H. Arimura
  • , T. Schram
  • , L. A. Ragnarsson
  • , A. Sibaja Hernandez
  • G. Hellings, N. Horiguchi, M. Heyns, G. Groeseneken, D. Linten, N. Collaert, A. Thean

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

We have shown that the poor PBTI reliability of IIIV/high-k gate stacks is universally related to process thermal budget limitations. Low temperature anneal optimization and high-k nitridation reduce oxide defect density. In contrast to a wide distribution of defect levels in Al2O3, HfO2 on InGaAs shows a minimum defect density ∼0.2eV below the channel EC. By introducing an interface dipole, a significant reliability boost was demonstrated. While low thermal budget high-k quality and IIIV interface thermal stability constitute challenges, our results show that a reliable IIIV/high-k gate stack can be fabricated.

Original languageEnglish
Title of host publication2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509006373
DOIs
Publication statusPublished - 21 Sep 2016
Externally publishedYes
Event36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, United States
Duration: 13 Jun 201616 Jun 2016

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2016-September
ISSN (Print)0743-1562

Conference

Conference36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
Country/TerritoryUnited States
CityHonolulu
Period13/06/1616/06/16

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