TY - GEN
T1 - Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations
AU - Chen, Jiaoyan
AU - Vasudevan, Dilip
AU - Popovici, Emanuel
AU - Schellekens, Michel
AU - Gillen, Peter
PY - 2010
Y1 - 2010
N2 - Leakage power is becoming the dominant power domponent in deep submicron technology and stability of the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced feature sizes. A novel 8T SRAM cell design considering these leakage and stability issues is proposed in this paper. Higher read static noise margin (SNM) compared to conventional 6T SRAM is achieved. The proposed SRAM is compared with a recently reported low power 8T,9T designs and the conventional 6T SRAM. Lower area compared to the 9T design and lower power consumption compared to conventional 6T, 8T and the 9T designs are reported. The adiabatic operation of this design provides further reduction in power compared to the non-adiabatic operation. The average power of the designs with process variation at 65 and 45nm processes are also reported. Power reduction of the order of 10 times (90-91 %) is reported with the proposed design.
AB - Leakage power is becoming the dominant power domponent in deep submicron technology and stability of the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced feature sizes. A novel 8T SRAM cell design considering these leakage and stability issues is proposed in this paper. Higher read static noise margin (SNM) compared to conventional 6T SRAM is achieved. The proposed SRAM is compared with a recently reported low power 8T,9T designs and the conventional 6T SRAM. Lower area compared to the 9T design and lower power consumption compared to conventional 6T, 8T and the 9T designs are reported. The adiabatic operation of this design provides further reduction in power compared to the non-adiabatic operation. The average power of the designs with process variation at 65 and 45nm processes are also reported. Power reduction of the order of 10 times (90-91 %) is reported with the proposed design.
UR - https://www.scopus.com/pages/publications/79953102283
U2 - 10.1109/ICECS.2010.5724542
DO - 10.1109/ICECS.2010.5724542
M3 - Conference proceeding
AN - SCOPUS:79953102283
SN - 9781424481576
T3 - 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings
SP - 434
EP - 437
BT - 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings
T2 - 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010
Y2 - 12 December 2010 through 15 December 2010
ER -