TY - GEN
T1 - Design and FPGA Implementation of Matrix Multiplier Using DEMUX-RCA-Based Vedic Multiplier
AU - Kumar, Balivada Yashwant
AU - Kharwar, Saurabh
AU - Singh, Sangeeta
AU - Mohammed, Mustafa K.A.
AU - Dauwed, Mohammed
N1 - Publisher Copyright:
© 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.
PY - 2023
Y1 - 2023
N2 - Matrix multiplication is a common technique for increasing the computational speed of scientific and engineering tasks. The matrix multiplier is designed in this paper utilizing an optimized Vedic multiplier. Vedic mathematics, which is a collection of sutras for doing mathematical arithmetic simply and more speedily, is utilized to speed up multiplication. These sutras aid in the reduction of several processors performance metrics, such as power and delay. As a result, the current multiplier approaches are replaced with Urdhva Tiriyagbhyam, a Vedic Math multiplication methodology. We used 1:8 demultiplexer-based Full Adders (DFAs) to create the Vedic Multiplier to circumvent the power constraint. As a result, the overall power of matrix multiplication was improved across various bits. The Optimized Matrix multiplier is designed in Verilog HDL, and the Nexys DDR4 of the Artix-7 series is utilized as the target device for synthesis.
AB - Matrix multiplication is a common technique for increasing the computational speed of scientific and engineering tasks. The matrix multiplier is designed in this paper utilizing an optimized Vedic multiplier. Vedic mathematics, which is a collection of sutras for doing mathematical arithmetic simply and more speedily, is utilized to speed up multiplication. These sutras aid in the reduction of several processors performance metrics, such as power and delay. As a result, the current multiplier approaches are replaced with Urdhva Tiriyagbhyam, a Vedic Math multiplication methodology. We used 1:8 demultiplexer-based Full Adders (DFAs) to create the Vedic Multiplier to circumvent the power constraint. As a result, the overall power of matrix multiplication was improved across various bits. The Optimized Matrix multiplier is designed in Verilog HDL, and the Nexys DDR4 of the Artix-7 series is utilized as the target device for synthesis.
KW - Demultiplexer
KW - Full adders
KW - Matrix multiplier
KW - Urdhva Tiryagbhyam Sutra
KW - Vedic multiplier
UR - https://www.scopus.com/pages/publications/85144966632
U2 - 10.1007/978-3-031-20429-6_21
DO - 10.1007/978-3-031-20429-6_21
M3 - Conference proceeding
AN - SCOPUS:85144966632
SN - 9783031204289
T3 - Lecture Notes in Networks and Systems
SP - 216
EP - 224
BT - Proceedings of the 2nd International Conference on Emerging Technologies and Intelligent Systems - ICETIS 2022
A2 - Al-Sharafi, Mohammed A.
A2 - Al-Emran, Mostafa
A2 - Shaalan, Khaled
A2 - Al-Kabi, Mohammed Naji
PB - Springer Science and Business Media Deutschland GmbH
T2 - 2nd International Conference on Emerging Technologies and Intelligent Systems, ICETIS 2022
Y2 - 2 September 2022 through 3 September 2022
ER -