Design and Implementation of Modified Vedic Multiplier Using Modified Decoder-Based Adder

Low power design has attracted much attention since the energy dissipation is a significant factor in digital integrated circuit design. A multiplier is one of the arithmetic circuits, which plays a major role in many computational systems based on the real time applications. The power consumption in the systems greatly depends on the power consumption of its multiplier. In this digitalization era, it becomes necessary to increase the speed of the digital circuits while reducing on-chip area and memory consumption. Vedic architectures have advantages in partial product generation and additions, which are done concurrently. In this research, slice LUT’s and power of the proposed 2 × 2 and 4 × 4 novel decoder based Vedic multiplier using Urdhva Tiryakbhayam sutra are calculated and compared with conventional multiplier. Therefore, utilizing the advantages of Vedic architectures with the proposed idea to solve the problem of balancing power consumption and speed increase in circuits. The simulations carried out and synthesis of the proposed 2 × 2 bit and 4 × 4 bit multiplier has been implemented using artex-7 on Xilinx Vivado. The results of the proposed Vedic multiplier with existing Vedic multiplier exhibits a significant improvement in term of resource utilization.