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Design and optimisation of a high current, high frequency monolithic buck converter

  • Jason Hannon
  • , Dara O'Sullivan
  • , Raymond Foley
  • , James Griffiths
  • , Kevin G. McCarthy
  • , Michael G. Egan

Research output: Chapter in Book/Report/Conference proceedingsConference proceedingpeer-review

Abstract

The detailed design and optimisation of a high current monolithic point-of-load (POL) buck converter is presented in this paper. The approach taken is to identify the major design issues which account for power losses and represent them as a function of the power device width. Having identified these loss sources and quantified them, the optimum power device sizes are obtained for a converter with a 20 MHz switching frequency.

Original languageEnglish
Title of host publication2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
Pages1472-1476
Number of pages5
DOIs
Publication statusPublished - 2008
Event2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC - Austin, TX, United States
Duration: 24 Feb 200828 Feb 2008

Publication series

NameConference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Conference

Conference2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
Country/TerritoryUnited States
CityAustin, TX
Period24/02/0828/02/08

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