Design considerations for multi-chip module silicon-photonic transceivers

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

High bandwidth density silicon photonic interconnects offer the potential to address the massive increase in bandwidth demands for data center traffic and high performance computing. One of the major challenges in realizing silicon photonics transceivers is the integration and packing of photonic ICs (PIC) with electronic ICs (EIC). This paper presents our version one, 2.5D integrated multi-chip module (MCM) transceiver for 4 channel wavelength division multiplexing (WDM) operation, targeting 10 Gbps per channel. We identify five key areas critical to successful integration of MCM transceivers, which we have used in developing our version two MCM transceiver: integration architecture, equivalent circuit model development, PIC to EIC interface modelling, MCM I/O design, and design for assembly.

Original languageEnglish
Title of host publicationMetro and Data Center Optical Networks and Short-Reach Links III
EditorsAtul K. Srivastava, Madeleine Glick, Youichi Akasaka
PublisherSPIE
ISBN (Electronic)9781510633797
DOIs
Publication statusPublished - 2020
EventMetro and Data Center Optical Networks and Short-Reach Links III 2020 - San Francisco, United States
Duration: 5 Feb 20206 Feb 2020

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Volume11308
ISSN (Print)0277-786X
ISSN (Electronic)1996-756X

Conference

ConferenceMetro and Data Center Optical Networks and Short-Reach Links III 2020
Country/TerritoryUnited States
CitySan Francisco
Period5/02/206/02/20

Keywords

  • 2.5D Integration
  • Interposer
  • Multi-Chip Module
  • Optical Interconnects
  • Silicon Photonics
  • Wavelength Division Multiplexing

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