@inproceedings{149fedb81c334a72af93093172b2725b,
title = "Design of a low power, sub-threshold, asynchronous arithmetic Logic Unit using a bidirectional adder",
abstract = "A novel asynchronous bidirectional arithmetic Logic Unit (ALU) is introduced in this paper. The adder in the proposed design is a ripple carry adder with the bidirectional characteristic. The ALU is designed with asynchronous dual rail circuit style. Several ALUs with sizes ranging from 4bits to 32 bits were built. Their power and performance metrics were compared with the conventional ALUs built with the fast adders designed with dynamic logic style. Significant power reduction with the sub-threshold operating voltage is achieved. Also the design is compared with the ALU design proposed for reversible quantum computers in the CMOS context to show the logic efficiency of the proposed design around 30 \% in area. Power reduction of 9-26\% was achieved for the addition operation and and 19.5 - 75.1\% for the logical operation on the proposed 32 bit ALU, compared to the conventional dynamic logic based ALU operated over the voltage range 0.2-0.3V.{"}",
keywords = "Adder, Arithmetic Logic Unit (ALU), Asynchronous design, Leakage and dynamic power, Reversible design",
author = "Jiaoyan Chen and Dilip Vasudevan and Emanuel Popovici and Michel Schellekens",
year = "2011",
doi = "10.1109/DSD.2011.44",
language = "English",
isbn = "9780769544946",
series = "Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011",
pages = "301--308",
booktitle = "Proceedings - 2011 14th Euromicro Conference on Digital System Design",
note = "2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011 ; Conference date: 31-08-2011 Through 02-09-2011",
}