Design of a reversible ripple carry adder for Excess-3 code

One of the main characteristic in VLSI circuits is power dissipation. Due to the information loss, conventional logic circuits result in energy dissipation. Reversible circuits because they do not lose information, have zero internal power dissipation. This paper proposes a reversible 4-bit parallel adder for Excess-3 code. Excess-3 is an unweighted and self-complementing code. Excess-3 coding over BCD coding has various advantages. The primary superiority is that a decimal number can be nines' complemented (for subtraction) as facilely as a binary number can be ones' complemented by inverting all bits. The proposed Excess-3 adder in the number of reversible gates and garbage outputs, allowing high-speed and low-power reversible circuits, covers all favorable characteristics of reversible circuits.