@inbook{fdc646fac9f040879004608866e63da4,
title = "Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS",
abstract = "We1 present an analog front end for a PAM-4 clock and data recovery circuit designed in 65nm CMOS. The front end consists of an arrangement of 8 interleaved master and slave sample-and-hold circuits, to be followed by an array of dynamic comparators. Each interleaved channel contains two wideband buffers with accurate bias and common-mode control circuitry to drive the sample-and-hold circuits. The worst-case (across process, temperature and supply voltage corners) aperture time of the sampling front end is 17ps for a differential input voltage swing of 200mV, sufficient to resolve a 56Gb/s (28Gbaud) PAM-4 signal. The power consumption is 55mW from 1.0V and 1.2V supply voltages.",
keywords = "Analog front end, PAM-4, pulse-amplitude modulation, serial link, transceiver",
author = "Sadeghipour, \{Khosrov D.\} and Townsend, \{Paul D.\} and Peter Ossieur",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Symposium on Circuits and Systems, ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",
year = "2015",
month = jul,
day = "27",
doi = "10.1109/ISCAS.2015.7168956",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1606--1609",
booktitle = "2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015",
address = "United States",
}