@inbook{cabffbd16edf4b35aad08fffa8f0d273,
title = "Design of Low-Voltage and Low-Power Cryogenic CMOS Voltage Reference Circuits",
abstract = "This paper presents the design of low-voltage and low-power cryogenic CMOS voltage reference circuits. This cryo-optimized circuit uses low-threshold devices to compensate for the transistors' threshold increase in ultra-low temperatures. Similarly, the PTAT factor is increased three times from its optimal value as compensation for the current decrease in cryogenic temperatures. A family of reference circuits was implemented in standard 65-nm CMOS. The silicon results show temperature coefficients of 419, 350, and 229 ppm/K in the ultra-wide temperature range from 4 to 295 K, with power consumptions at 4 K of only 5.3 μ W, 22.7μ W, and 410 nW, respectively.",
keywords = "Bulk CMOS, Circuit, Cryo-optimized, Cryogenic, Design, Quantum-Computing, Reference",
author = "Minda Wen and Mccarthy, \{Kevin G.\} and Ivan O'Connel and Salgado, \{Gerardo Molina\}",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 67th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2024 ; Conference date: 11-08-2024 Through 14-08-2024",
year = "2024",
doi = "10.1109/MWSCAS60917.2024.10658845",
language = "English",
series = "Midwest Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1016--1020",
booktitle = "2024 IEEE 67th International Midwest Symposium on Circuits and Systems, MWSCAS 2024",
address = "United States",
}