Development and application of a macro model for Flash EEPROM design

Mike O’shea; Ann Concannon; Kevin McCarthy; Bill Lane; Alan Mathewson; Michiel Slotboom

doi:10.1109/ASIC.2000.880700

Development and application of a macro model for Flash EEPROM design

Mike O’shea
, Ann Concannon
, Kevin McCarthy
, Bill Lane
, Alan Mathewson
, Michiel Slotboom

School of Engineering and Architecture

Koninklijke Philips N.V.

Research output: Contribution to journal › Article › peer-review

Abstract

The inclusion of embedded Flash memory in systems-on-chip designs enables the addition of many new features. However to enable designers to embed Flash memory in an efficient and competent manner, they must have the capability to simulate full circuit operation. Therefore a flexible Flash EEPROM model is required. An accurate and numerically efficient model for the transient and DC characteristics of Fowler Nordheim (FN) based Flash EEPROM cells has been developed. The model has been extensively validated, using read, program and erase operations. The model has also been applied to several applications, in a typical structure. These display the ability of the model to accelerate the design cycle for applications which require Flash memory.

Original language	English
Pages (from-to)	192-196
Number of pages	5
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs	https://doi.org/10.1109/ASIC.2000.880700
Publication status	Published - 2000

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AB - The inclusion of embedded Flash memory in systems-on-chip designs enables the addition of many new features. However to enable designers to embed Flash memory in an efficient and competent manner, they must have the capability to simulate full circuit operation. Therefore a flexible Flash EEPROM model is required. An accurate and numerically efficient model for the transient and DC characteristics of Fowler Nordheim (FN) based Flash EEPROM cells has been developed. The model has been extensively validated, using read, program and erase operations. The model has also been applied to several applications, in a typical structure. These display the ability of the model to accelerate the design cycle for applications which require Flash memory.

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JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

ER -

Development and application of a macro model for Flash EEPROM design

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