Device design and estimated performance for p-type junctionless transistors on bulk germanium substrates

The junctionless nanowire transistor (JNT) has recently been demonstrated to be a promising device for sub-20-nm nodes. So far, most devices were made on semiconductor-on-insulator substrates. The aim of this work is to evaluate the concept of multigate germanium (Ge) JNTs on bulk substrates, using a dedicated modeling methodology. The variation of device performance due to geometry, channel, and substrate doping concentrations is discussed and proposed as a guideline for designing p-type Ge bulk JNTs. This work shows that a potential barrier is formed in the substrate by the p-n junction that isolates the channel from the substrate, and an effective confinement of current in the nanowire can be achieved. The Ge bulk JNT facilitates excellent scalability. Our modeling predicts that, for a gate length of 16 nm, a subthreshold slope of 77 mV/dec and a drain-induced barrier lowering of 70 mV can be obtained with an I _on/I _off current ratio of 1.1 × 10 ⁵.