Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

S. Severi; K. G. Anil; J. B. Pawlak; R. Duffy; K. Henson; R. Lindsay; A. Lauwers; A. Veloso; J. F. De Marneffe; J. Ramos; R. A. Camillo-Castillo; P. Eyben; C. Dachs; W. Vandervost; M. Jurczak; S. Biesemans; K. De Meyer

Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

S. Severi
, K. G. Anil
, J. B. Pawlak
, R. Duffy
, K. Henson
, R. Lindsay
, A. Lauwers
, A. Veloso
, J. F. De Marneffe
, J. Ramos
, R. A. Camillo-Castillo
, P. Eyben
, C. Dachs
, W. Vandervost
, M. Jurczak
, S. Biesemans
, K. De Meyer

Research output: Contribution to journal › Article › peer-review

Abstract

This paper reports on the successful integration of truly diffusion-less (less-than-650°C) junction formation by SPER in pMOSFETs in combination with Ni-FUSI gates for the first time. The obtained drive currents are 355 μA/μm for an off-state of 10 pA/μm at Vdd=-1.2V and 1.4nm EOT SiON. We demonstrate that the gate de-activation problem associated with SPER is effectively solved by the use of the FUSI gate electrode. Super halo profiles are obtained with SPER, which opens up the halo design space for accurate SCE control. The junction leakage is greatly reduced by engineering the damage region away from the junction depletion region.

Original language	English
Pages (from-to)	99-102
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 2004
Externally published	Yes
Event	IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States Duration: 13 Dec 2004 → 15 Dec 2004

Cite this

Severi, S., Anil, K. G., Pawlak, J. B., Duffy, R., Henson, K., Lindsay, R., Lauwers, A., Veloso, A., De Marneffe, J. F., Ramos, J., Camillo-Castillo, R. A., Eyben, P., Dachs, C., Vandervost, W., Jurczak, M., Biesemans, S., & De Meyer, K. (2004). Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices. Technical Digest - International Electron Devices Meeting, 99-102.

@article{0855e11c656441319cb8a1ba9204ee34,

title = "Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices",

abstract = "This paper reports on the successful integration of truly diffusion-less (less-than-650°C) junction formation by SPER in pMOSFETs in combination with Ni-FUSI gates for the first time. The obtained drive currents are 355 μA/μm for an off-state of 10 pA/μm at Vdd=-1.2V and 1.4nm EOT SiON. We demonstrate that the gate de-activation problem associated with SPER is effectively solved by the use of the FUSI gate electrode. Super halo profiles are obtained with SPER, which opens up the halo design space for accurate SCE control. The junction leakage is greatly reduced by engineering the damage region away from the junction depletion region.",

author = "S. Severi and Anil, \{K. G.\} and Pawlak, \{J. B.\} and R. Duffy and K. Henson and R. Lindsay and A. Lauwers and A. Veloso and \{De Marneffe\}, \{J. F.\} and J. Ramos and Camillo-Castillo, \{R. A.\} and P. Eyben and C. Dachs and W. Vandervost and M. Jurczak and S. Biesemans and \{De Meyer\}, K.",

year = "2004",

language = "English",

pages = "99--102",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Electron Devices Meeting, 2004 IEDM ; Conference date: 13-12-2004 Through 15-12-2004",

}

Severi, S, Anil, KG, Pawlak, JB, Duffy, R, Henson, K, Lindsay, R, Lauwers, A, Veloso, A, De Marneffe, JF, Ramos, J, Camillo-Castillo, RA, Eyben, P, Dachs, C, Vandervost, W, Jurczak, M, Biesemans, S & De Meyer, K 2004, 'Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices', Technical Digest - International Electron Devices Meeting, pp. 99-102.

TY - JOUR

T1 - Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

AU - Severi, S.

AU - Anil, K. G.

AU - Pawlak, J. B.

AU - Duffy, R.

AU - Henson, K.

AU - Lindsay, R.

AU - Lauwers, A.

AU - Veloso, A.

AU - De Marneffe, J. F.

AU - Ramos, J.

AU - Camillo-Castillo, R. A.

AU - Eyben, P.

AU - Dachs, C.

AU - Vandervost, W.

AU - Jurczak, M.

AU - Biesemans, S.

AU - De Meyer, K.

PY - 2004

Y1 - 2004

N2 - This paper reports on the successful integration of truly diffusion-less (less-than-650°C) junction formation by SPER in pMOSFETs in combination with Ni-FUSI gates for the first time. The obtained drive currents are 355 μA/μm for an off-state of 10 pA/μm at Vdd=-1.2V and 1.4nm EOT SiON. We demonstrate that the gate de-activation problem associated with SPER is effectively solved by the use of the FUSI gate electrode. Super halo profiles are obtained with SPER, which opens up the halo design space for accurate SCE control. The junction leakage is greatly reduced by engineering the damage region away from the junction depletion region.

AB - This paper reports on the successful integration of truly diffusion-less (less-than-650°C) junction formation by SPER in pMOSFETs in combination with Ni-FUSI gates for the first time. The obtained drive currents are 355 μA/μm for an off-state of 10 pA/μm at Vdd=-1.2V and 1.4nm EOT SiON. We demonstrate that the gate de-activation problem associated with SPER is effectively solved by the use of the FUSI gate electrode. Super halo profiles are obtained with SPER, which opens up the halo design space for accurate SCE control. The junction leakage is greatly reduced by engineering the damage region away from the junction depletion region.

UR - https://www.scopus.com/pages/publications/21644473099

M3 - Article

AN - SCOPUS:21644473099

SN - 0163-1918

SP - 99

EP - 102

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting, 2004 IEDM

Y2 - 13 December 2004 through 15 December 2004

ER -

Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

Abstract

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