@inbook{763da2cbfdef4bdc8b0e58d38937670c,
title = "Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration",
abstract = "We are proposing a double gate junction-less device with a processing temperature compatible with state-of-the-art dense low k dielectric back-end of line copper process. The thermal stability of the back-end of line process was studied, showing no degradation for an anneal temperature up to 500°C 1h. Using wafer bonding, a crystalline silicon layer can be transferred onto a carrier wafer followed by top device processing at low temperature with a gate first approach as well as direct W contacts with Ti/TiN barrier layer. To avoid dopant activation using high temperature anneal (spike), junction-less devices are used, where the uniform channel dopant implantation and activation can be done prior to the layer transfer.",
keywords = "Cu BEOL, junction-less devices, sequential 3D, wafer bonding",
author = "A. Vandooren and L. Witters and E. Vecchio and E. Kunnen and G. Hellings and L. Peng and F. Inoue and W. Li and N. Waldron and D. Mocuta and N. Collaert",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 ; Conference date: 16-10-2017 Through 18-10-2017",
year = "2017",
month = jul,
day = "2",
doi = "10.1109/S3S.2017.8309234",
language = "English",
series = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--2",
booktitle = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",
address = "United States",
}