Effect of amorphization on activation and deactivation of boron in source/drain, channel and poly gate

For the 45nm technology node alternative approaches to conventional spike anneals are investigated. Especially solid phase epitaxial regrowth (SPER) is seriously considered. In this work, we investigate the effect of Ge amorphization and low temperature regrowth on the activation and deactivation of boron in source and drain region, transistor channel and polycrystalline gate. 2D electrical profiles (SSRM) indicate active and non-active regions at the transistor cross-section. From studies on blanket wafers we demonstrate that: Significant enhancement (more that 20%) of boron extension activation by SPER can be achieved by fast ramp-up rates up to 500 °C/s compared to slow ones 40 °C/s. Due to the high density of Si_i in the End-Of-Range (EOR) region their dissolution at temperatures above 750 °C deactivates the junctions [1], The deactivation process and thermal reactivation are well understood theoretically and can be modeled accurately [2]. Amorphization of transistor channel followed by SPER creates B-Si_i clusters in the EOR region. A significant part of the transistor channel is strongly deactivated and its full recovery after anneals at higher temperatures is not possible because of efficient boron migration. Boron diffusion inside silicon bulk lowers R_s. In that way the role of pocket implants is diminished due to boron redistribution. Deactivation of low a concentration boron profiles has been successfully modeled by Aboy et al. [3]. Amorphized poly silicon material requires significantly higher thermal budget for regrowth and boron activation than amorphized crystalline Si. Randomly oriented poly grains are characterized by reduced regrowth speed due to various crystalline orientations. X-TEM and R_s analysis provide evidence that reactivation of poly silicon material is non-uniform across the wafer. It is concluded that amorphization of silicon offers significant advantages for boron activation enhancement and junction depth control. Simultaneously it introduces problems related to channel deactivation and partially activated poly. Fundamental understanding of these issues enables further optimization of transistor integration.