Effects of the Interfacial Layer on the Leakage Current and Hysteresis Behaviour of Ferroelectric Devices

Data collected from electrical characterization on Metal - Ferroelectric - Insulator - Semiconductor (MFIS) and Metal- Ferroelectric - Metal (MIM) Ferroelectric (FE) devices are compared. Although numerous studies exist on both device structures, a direct comparison of the differences in the signatures of degradation during electrical characterization is lacking. In this work, analysis of Interrupted CVS and transient current measurements using the PUND waveform alongside pulsed cycling stress indicate that the interfacial layer (IL) in the MFIS structure is the origin of the discrepancies and that the IL influences the collected data through increasing charge trapping and defect generation, as well as modifying the band energy diagram of the device stack. The qualitative studies of electrical characterization data provide a starting point for quantitative analysis and identification of the physical mechanisms underlying the observed degradation.