TY - GEN
T1 - Efficient architectures and implementation of arithmetic functions approximation based stochastic computing
AU - Luong, Tieu Khanh
AU - Nguyen, Van Tinh
AU - Nguyen, Anh Thai
AU - Popovici, Emanuel
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Stochastic computing (SC) has emerged as a potential alternative to binary computing for a number of low-power embedded systems, DSP, neural networks and communications applications. In this paper, a new method, associated architectures and implementations of complex arithmetic functions, such as exponential, sigmoid and hyperbolic tangent functions are presented. Our approach is based on a combination of piecewise linear (PWL) approximation as well as a polynomial interpolation based (Lagrange interpolation) methods. The proposed method aims at reducing the number of binary to stochastic converters. This is the most power sensitive module in an SC system. The hardware implementation for each complex arithmetic function is then derived using the 65nm CMOS technology node. In terms of accuracy, the proposed approach outperforms other well-known methods by 2 times on average. The power consumption of the implementations based on our method is decreased on average by 40 % comparing to other previous solutions. Additionally, the hardware complexity of our proposed method is also improved (40 % on average) while the critical path of the proposed method is slightly increased by 2.5% on average when comparing to other methods.
AB - Stochastic computing (SC) has emerged as a potential alternative to binary computing for a number of low-power embedded systems, DSP, neural networks and communications applications. In this paper, a new method, associated architectures and implementations of complex arithmetic functions, such as exponential, sigmoid and hyperbolic tangent functions are presented. Our approach is based on a combination of piecewise linear (PWL) approximation as well as a polynomial interpolation based (Lagrange interpolation) methods. The proposed method aims at reducing the number of binary to stochastic converters. This is the most power sensitive module in an SC system. The hardware implementation for each complex arithmetic function is then derived using the 65nm CMOS technology node. In terms of accuracy, the proposed approach outperforms other well-known methods by 2 times on average. The power consumption of the implementations based on our method is decreased on average by 40 % comparing to other previous solutions. Additionally, the hardware complexity of our proposed method is also improved (40 % on average) while the critical path of the proposed method is slightly increased by 2.5% on average when comparing to other methods.
KW - Arithmetic
KW - Efficient architectures
KW - Lagrange interpolations
KW - Low Power
KW - Piecewise linear approximation
KW - Sigmoid function
KW - Stochastic computing
KW - VLSI
UR - https://www.scopus.com/pages/publications/85072615485
U2 - 10.1109/ASAP.2019.00018
DO - 10.1109/ASAP.2019.00018
M3 - Conference proceeding
AN - SCOPUS:85072615485
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 281
EP - 287
BT - Proceedings - 2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 30th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019
Y2 - 15 July 2019 through 17 July 2019
ER -