TY - GEN
T1 - Efficient Berlekamp-Massey based recursive decoder for Reed-Solomon codes
AU - Srivastava, Shraddha
AU - McSweeney, Richard
AU - Spagnol, Christian
AU - Popovici, Emanuel
PY - 2012
Y1 - 2012
N2 - This paper presents a high speed low complexity algorithm and architecture for encoding and decoding Reed-Solomon (RS) codes based on evaluation. The recursive use of discrepancy computation step of Berlekamp-Massey (BM) algorithm leads directly to the computation of message symbols without using Chien Search and Forney's Formula, making the circuitry much simpler for proposed decoder as compared to the classical decoder. Also, the proposed scheme requires less clock cycles compared to the classical decoder leading to reduced energy consumption. In order to make a fair comparison, classical and proposed decoder for RS codes over the field F 256 has been implemented on TSMC 65nm ASIC process using some arithmetic units. For RS(255, 239) code, the proposed decoder has a total cell count of 16075 which results in a reduction of 57.6% in hardware area as compared to classical decoder. Also, 53.07% timing reduction is obtained with the proposed decoder.
AB - This paper presents a high speed low complexity algorithm and architecture for encoding and decoding Reed-Solomon (RS) codes based on evaluation. The recursive use of discrepancy computation step of Berlekamp-Massey (BM) algorithm leads directly to the computation of message symbols without using Chien Search and Forney's Formula, making the circuitry much simpler for proposed decoder as compared to the classical decoder. Also, the proposed scheme requires less clock cycles compared to the classical decoder leading to reduced energy consumption. In order to make a fair comparison, classical and proposed decoder for RS codes over the field F 256 has been implemented on TSMC 65nm ASIC process using some arithmetic units. For RS(255, 239) code, the proposed decoder has a total cell count of 16075 which results in a reduction of 57.6% in hardware area as compared to classical decoder. Also, 53.07% timing reduction is obtained with the proposed decoder.
KW - evaluation
KW - High speed
KW - low complexity
KW - recursive
KW - Reed-Solomon codeć
UR - https://www.scopus.com/pages/publications/84864255506
U2 - 10.1109/MIEL.2012.6222879
DO - 10.1109/MIEL.2012.6222879
M3 - Conference proceeding
AN - SCOPUS:84864255506
SN - 9781467302388
T3 - 2012 28th International Conference on Microelectronics - Proceedings, MIEL 2012
SP - 379
EP - 382
BT - 2012 28th International Conference on Microelectronics - Proceedings, MIEL 2012
T2 - 2012 28th International Conference on Microelectronics, MIEL 2012
Y2 - 13 May 2012 through 16 May 2012
ER -