Efficient hardware for the tate pairing calculation in characteristic three

T. Kerins; W. P. Marnane; E. M. Popovici; P. S.L.M. Barreto

doi:10.1007/11545262_30

Efficient hardware for the tate pairing calculation in characteristic three

T. Kerins
, W. P. Marnane
, E. M. Popovici
, P. S.L.M. Barreto

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(3^6m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF(3^m). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed.

Original language	English
Pages (from-to)	412-426
Number of pages	15
Journal	Lecture Notes in Computer Science
Volume	3659
DOIs	https://doi.org/10.1007/11545262_30
Publication status	Published - 2005
Event	7th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2005 - Edinburgh, United Kingdom Duration: 29 Aug 2005 → 1 Sep 2005

Keywords

Characteristic three
Hardware accelerator
Tate pairing
Tower fields

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10.1007/11545262_30

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title = "Efficient hardware for the tate pairing calculation in characteristic three",

abstract = "In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(36m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF(3m). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed.",

keywords = "Characteristic three, Hardware accelerator, Tate pairing, Tower fields",

author = "T. Kerins and Marnane, \{W. P.\} and Popovici, \{E. M.\} and Barreto, \{P. S.L.M.\}",

year = "2005",

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journal = "Lecture Notes in Computer Science",

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AU - Popovici, E. M.

AU - Barreto, P. S.L.M.

PY - 2005

Y1 - 2005

N2 - In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(36m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF(3m). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed.

AB - In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(36m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF(3m). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed.

KW - Characteristic three

KW - Hardware accelerator

KW - Tate pairing

KW - Tower fields

UR - https://www.scopus.com/pages/publications/27244434197

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JF - Lecture Notes in Computer Science

T2 - 7th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2005

Y2 - 29 August 2005 through 1 September 2005

ER -

Efficient hardware for the tate pairing calculation in characteristic three

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Keywords

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