Efficient Parameter Extraction and Statistical Analysis for a 0.25um low-power CMOS Process

E. V. Saavedra Diaz; K. G. McCarthy; D. B.M. Klaassen; A. Mathewson

doi:10.1109/ESSDERC.1997.194514

Efficient Parameter Extraction and Statistical Analysis for a 0.25um low-power CMOS Process

E. V. Saavedra Diaz
, K. G. McCarthy
, D. B.M. Klaassen
, A. Mathewson

School of Engineering and Architecture

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

An efficient parameter extraction strategy suitable for deep submicron CMOS processes is presented. This has been applied to generate a statistical parameter database for a 0.25 micron process and to generate best and worst case models for circuit simulation by means of Principal Component Analysis.

Original language	English
Title of host publication	European Solid-State Device Research Conference
Editors	H. Grunbacher
Publisher	IEEE Computer Society
Pages	656-659
Number of pages	4
ISBN (Electronic)	2863322214
DOIs	https://doi.org/10.1109/ESSDERC.1997.194514
Publication status	Published - 1997
Event	27th European Solid-State Device Research Conference, ESSDERC 1997 - Stuttgart, Germany Duration: 22 Sep 1997 → 24 Sep 1997

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Conference

Conference	27th European Solid-State Device Research Conference, ESSDERC 1997
Country/Territory	Germany
City	Stuttgart
Period	22/09/97 → 24/09/97

Access to Document

10.1109/ESSDERC.1997.194514

Cite this

Saavedra Diaz, E. V., McCarthy, K. G., Klaassen, D. B. M., & Mathewson, A. (1997). Efficient Parameter Extraction and Statistical Analysis for a 0.25um low-power CMOS Process. In H. Grunbacher (Ed.), European Solid-State Device Research Conference (pp. 656-659). (European Solid-State Device Research Conference). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.1997.194514

@inbook{4044476c5b9448ed891559725145b90a,

title = "Efficient Parameter Extraction and Statistical Analysis for a 0.25um low-power CMOS Process",

abstract = "An efficient parameter extraction strategy suitable for deep submicron CMOS processes is presented. This has been applied to generate a statistical parameter database for a 0.25 micron process and to generate best and worst case models for circuit simulation by means of Principal Component Analysis.",

author = "\{Saavedra Diaz\}, \{E. V.\} and McCarthy, \{K. G.\} and Klaassen, \{D. B.M.\} and A. Mathewson",

year = "1997",

doi = "10.1109/ESSDERC.1997.194514",

language = "English",

series = "European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

pages = "656--659",

editor = "H. Grunbacher",

booktitle = "European Solid-State Device Research Conference",

address = "United States",

note = "27th European Solid-State Device Research Conference, ESSDERC 1997 ; Conference date: 22-09-1997 Through 24-09-1997",

}

Saavedra Diaz, EV, McCarthy, KG, Klaassen, DBM & Mathewson, A 1997, Efficient Parameter Extraction and Statistical Analysis for a 0.25um low-power CMOS Process. in H Grunbacher (ed.), European Solid-State Device Research Conference. European Solid-State Device Research Conference, IEEE Computer Society, pp. 656-659, 27th European Solid-State Device Research Conference, ESSDERC 1997, Stuttgart, Germany, 22/09/97. https://doi.org/10.1109/ESSDERC.1997.194514

Efficient Parameter Extraction and Statistical Analysis for a 0.25um low-power CMOS Process. / Saavedra Diaz, E. V.; McCarthy, K. G.; Klaassen, D. B.M. et al.
European Solid-State Device Research Conference. ed. / H. Grunbacher. IEEE Computer Society, 1997. p. 656-659 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - Efficient Parameter Extraction and Statistical Analysis for a 0.25um low-power CMOS Process

AU - Saavedra Diaz, E. V.

AU - McCarthy, K. G.

AU - Klaassen, D. B.M.

AU - Mathewson, A.

PY - 1997

Y1 - 1997

N2 - An efficient parameter extraction strategy suitable for deep submicron CMOS processes is presented. This has been applied to generate a statistical parameter database for a 0.25 micron process and to generate best and worst case models for circuit simulation by means of Principal Component Analysis.

AB - An efficient parameter extraction strategy suitable for deep submicron CMOS processes is presented. This has been applied to generate a statistical parameter database for a 0.25 micron process and to generate best and worst case models for circuit simulation by means of Principal Component Analysis.

UR - https://www.scopus.com/pages/publications/0001987549

U2 - 10.1109/ESSDERC.1997.194514

DO - 10.1109/ESSDERC.1997.194514

M3 - Chapter

AN - SCOPUS:0001987549

T3 - European Solid-State Device Research Conference

SP - 656

EP - 659

BT - European Solid-State Device Research Conference

A2 - Grunbacher, H.

PB - IEEE Computer Society

T2 - 27th European Solid-State Device Research Conference, ESSDERC 1997

Y2 - 22 September 1997 through 24 September 1997

ER -

Efficient Parameter Extraction and Statistical Analysis for a 0.25um low-power CMOS Process

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this