TY - CHAP
T1 - Efficient realization of probabilistic gradient descent bit flipping decoders
AU - Le, Khoa
AU - Declercq, David
AU - Ghaffari, Fakhreddine
AU - Spagnol, Christian
AU - Popovici, Emmanuel
AU - Ivanis, Predrag
AU - Vasic, Bane
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/7/27
Y1 - 2015/7/27
N2 - In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.
AB - In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.
KW - bit-flipping
KW - LDPC decoders
KW - PGDBF
KW - random generators
UR - https://www.scopus.com/pages/publications/84946203171
U2 - 10.1109/ISCAS.2015.7168928
DO - 10.1109/ISCAS.2015.7168928
M3 - Chapter
AN - SCOPUS:84946203171
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1494
EP - 1497
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -