Electron traps at sidewalls of vertical n+-GaAs/n--InGaP/p+-GaAs diodes detected with deep-level transient spectroscopy

  • Hao Yu
  • , Po Chun Brent Hsu
  • , Abhitosh Vais
  • , Eddy Simoen
  • , Niamh Waldron
  • , Nadine Collaert

Research output: Chapter in Book/Report/Conference proceedingsConference proceedingpeer-review

Abstract

Electron traps are detected from vertical n+-GaAs/n--InGaP/p+-GaAs diodes with deep-level transient spectroscopy (DLTS). Combining lock-in window (tw) varying DLTS and double-correlation DLTS (DDTLS), we assign the electron traps to surface states at the sidewalls of the diodes. The methodology is introduced in the paper.

Original languageEnglish
Title of host publication19th International Workshop on Junction Technology, IWJT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487277
DOIs
Publication statusPublished - Jun 2019
Externally publishedYes
Event19th International Workshop on Junction Technology, IWJT 2019 - Kyoto, Japan
Duration: 6 Jun 20197 Jun 2019

Publication series

Name19th International Workshop on Junction Technology, IWJT 2019

Conference

Conference19th International Workshop on Junction Technology, IWJT 2019
Country/TerritoryJapan
CityKyoto
Period6/06/197/06/19

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