Energy efficient elliptic curve processor

Maurice Keller; William Marnane

doi:10.1007/978-3-540-95948-9_29

Energy efficient elliptic curve processor

Maurice Keller
, William Marnane

University College Cork

Research output: Contribution to journal › Article › peer-review

Abstract

Elliptic curve cryptography is highly suited for implementation in resource constrained environments, however, dedicated hardware accelerators are necessary to provide the low power/energy security required in small, battery powered devices. This paper presents a low energy ASIC implementation of an elliptic curve processor which consumes minimal energy per point multiplication, thereby prolonging battery life in constrained devices. The energy/power/area trade-off is explored. In 0.13 μm CMOS technology the architecture consumes a minimum of 1.32μJ at 500 kHz using a digit size of 15 and 24.6 kgates.

Original language	English
Pages (from-to)	287-296
Number of pages	10
Journal	Lecture Notes in Computer Science
Volume	5349 LNCS
DOIs	https://doi.org/10.1007/978-3-540-95948-9_29
Publication status	Published - 2009
Event	18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008 - Lisbon, Portugal Duration: 10 Sep 2008 → 12 Sep 2008

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10.1007/978-3-540-95948-9_29

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abstract = "Elliptic curve cryptography is highly suited for implementation in resource constrained environments, however, dedicated hardware accelerators are necessary to provide the low power/energy security required in small, battery powered devices. This paper presents a low energy ASIC implementation of an elliptic curve processor which consumes minimal energy per point multiplication, thereby prolonging battery life in constrained devices. The energy/power/area trade-off is explored. In 0.13 μm CMOS technology the architecture consumes a minimum of 1.32μJ at 500 kHz using a digit size of 15 and 24.6 kgates.",

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AU - Marnane, William

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AB - Elliptic curve cryptography is highly suited for implementation in resource constrained environments, however, dedicated hardware accelerators are necessary to provide the low power/energy security required in small, battery powered devices. This paper presents a low energy ASIC implementation of an elliptic curve processor which consumes minimal energy per point multiplication, thereby prolonging battery life in constrained devices. The energy/power/area trade-off is explored. In 0.13 μm CMOS technology the architecture consumes a minimum of 1.32μJ at 500 kHz using a digit size of 15 and 24.6 kgates.

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DO - 10.1007/978-3-540-95948-9_29

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T2 - 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008

Y2 - 10 September 2008 through 12 September 2008

ER -

Energy efficient elliptic curve processor

Abstract

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