First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

A. Vandooren; J. Franco; Z. Wu; B. Parvais; W. Li; L. Witters; A. Walke; L. Peng; V. Deshpande; N. Rassoul; G. Hellings; G. Jamieson; F. Inoue; K. Devriendt; L. Teugels; N. Heylen; E. Vecchio; T. Zheng; E. Rosseel; W. Vanherle; A. Hikavyy; G. Mannaert; B. T. Chan; R. Ritzenthaler; J. Mitard; L. Ragnarsson; N. Waldron; V. De Heyn; S. Demuynck; J. Boemmels; D. Mocuta; J. Ryckaert; N. Collaert

doi:10.1109/IEDM.2018.8614654

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

A. Vandooren
, J. Franco
, Z. Wu
, B. Parvais
, W. Li
, L. Witters
, A. Walke
, L. Peng
, V. Deshpande
, N. Rassoul
, G. Hellings
, G. Jamieson
, F. Inoue
, K. Devriendt
, L. Teugels
, N. Heylen
, E. Vecchio
, T. Zheng
, E. Rosseel
, W. Vanherle

A. Hikavyy, G. Mannaert, B. T. Chan, R. Ritzenthaler, J. Mitard, L. Ragnarsson, N. Waldron, V. De Heyn, S. Demuynck, J. Boemmels, D. Mocuta, J. Ryckaert, N. Collaert

Interuniversitair Micro-Elektronica Centrum
KU Leuven
Vrije Universiteit Brussel

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature ( T 525 C) in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO₂ gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO_x dipole improves device performance and brings the BTI reliability within specification at low temperature.

Original language	English
Title of host publication	2018 IEEE International Electron Devices Meeting, IEDM 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	7.1.1-7.1.4
ISBN (Electronic)	9781728119878
DOIs	https://doi.org/10.1109/IEDM.2018.8614654
Publication status	Published - 2 Jul 2018
Externally published	Yes
Event	64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States Duration: 1 Dec 2018 → 5 Dec 2018

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2018-December
ISSN (Print)	0163-1918

Conference

Conference	64th Annual IEEE International Electron Devices Meeting, IEDM 2018
Country/Territory	United States
City	San Francisco
Period	1/12/18 → 5/12/18

Access to Document

10.1109/IEDM.2018.8614654

Cite this

Vandooren, A., Franco, J., Wu, Z., Parvais, B., Li, W., Witters, L., Walke, A., Peng, L., Deshpande, V., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., Rosseel, E., ... Collaert, N. (2018). First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers. In 2018 IEEE International Electron Devices Meeting, IEDM 2018 (pp. 7.1.1-7.1.4). Article 8614654 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614654

@inproceedings{ff980f22f13748ab8448ee292ac1ef16,

title = "First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers",

abstract = "3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature ( T 525 C) in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiOx dipole improves device performance and brings the BTI reliability within specification at low temperature.",

author = "A. Vandooren and J. Franco and Z. Wu and B. Parvais and W. Li and L. Witters and A. Walke and L. Peng and V. Deshpande and N. Rassoul and G. Hellings and G. Jamieson and F. Inoue and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and E. Rosseel and W. Vanherle and A. Hikavyy and G. Mannaert and Chan, \{B. T.\} and R. Ritzenthaler and J. Mitard and L. Ragnarsson and N. Waldron and \{De Heyn\}, V. and S. Demuynck and J. Boemmels and D. Mocuta and J. Ryckaert and N. Collaert",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 ; Conference date: 01-12-2018 Through 05-12-2018",

year = "2018",

month = jul,

day = "2",

doi = "10.1109/IEDM.2018.8614654",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "7.1.1--7.1.4",

booktitle = "2018 IEEE International Electron Devices Meeting, IEDM 2018",

address = "United States",

}

Vandooren, A, Franco, J, Wu, Z, Parvais, B, Li, W, Witters, L, Walke, A, Peng, L, Deshpande, V, Rassoul, N, Hellings, G, Jamieson, G, Inoue, F, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Rosseel, E, Vanherle, W, Hikavyy, A, Mannaert, G, Chan, BT, Ritzenthaler, R, Mitard, J, Ragnarsson, L, Waldron, N, De Heyn, V, Demuynck, S, Boemmels, J, Mocuta, D, Ryckaert, J & Collaert, N 2018, First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers. in 2018 IEEE International Electron Devices Meeting, IEDM 2018., 8614654, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2018-December, Institute of Electrical and Electronics Engineers Inc., pp. 7.1.1-7.1.4, 64th Annual IEEE International Electron Devices Meeting, IEDM 2018, San Francisco, United States, 1/12/18. https://doi.org/10.1109/IEDM.2018.8614654

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers. / Vandooren, A.; Franco, J.; Wu, Z. et al.
2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 7.1.1-7.1.4 8614654 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

AU - Vandooren, A.

AU - Franco, J.

AU - Wu, Z.

AU - Parvais, B.

AU - Li, W.

AU - Witters, L.

AU - Walke, A.

AU - Peng, L.

AU - Deshpande, V.

AU - Rassoul, N.

AU - Hellings, G.

AU - Jamieson, G.

AU - Inoue, F.

AU - Devriendt, K.

AU - Teugels, L.

AU - Heylen, N.

AU - Vecchio, E.

AU - Zheng, T.

AU - Rosseel, E.

AU - Vanherle, W.

AU - Hikavyy, A.

AU - Mannaert, G.

AU - Chan, B. T.

AU - Ritzenthaler, R.

AU - Mitard, J.

AU - Ragnarsson, L.

AU - Waldron, N.

AU - De Heyn, V.

AU - Demuynck, S.

AU - Boemmels, J.

AU - Mocuta, D.

AU - Ryckaert, J.

AU - Collaert, N.

PY - 2018/7/2

Y1 - 2018/7/2

N2 - 3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature ( T 525 C) in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiOx dipole improves device performance and brings the BTI reliability within specification at low temperature.

AB - 3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature ( T 525 C) in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiOx dipole improves device performance and brings the BTI reliability within specification at low temperature.

UR - https://www.scopus.com/pages/publications/85061772650

U2 - 10.1109/IEDM.2018.8614654

DO - 10.1109/IEDM.2018.8614654

M3 - Conference proceeding

AN - SCOPUS:85061772650

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 7.1.1-7.1.4

BT - 2018 IEEE International Electron Devices Meeting, IEDM 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 64th Annual IEEE International Electron Devices Meeting, IEDM 2018

Y2 - 1 December 2018 through 5 December 2018

ER -

Vandooren A, Franco J, Wu Z, Parvais B, Li W, Witters L et al. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers. In 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 7.1.1-7.1.4. 8614654. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2018.8614654

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

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