First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

E. Capogreco; L. Witters; H. Arimura; F. Sebaai; C. Porret; A. Hikavyy; R. Loo; A. P. Milenin; G. Eneman; P. Favia; H. Bender; K. Wostyn; E. Dentoni Litta; A. Schulze; C. Vrancken; A. Opdebeeck; J. Mitard; R. Langer; F. Holsteyns; N. Waldron; K. Barla; V. De Heyn; D. Mocuta; N. Collaert

doi:10.1109/VLSIT.2018.8510645

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

E. Capogreco
, L. Witters
, H. Arimura
, F. Sebaai
, C. Porret
, A. Hikavyy
, R. Loo
, A. P. Milenin
, G. Eneman
, P. Favia
, H. Bender
, K. Wostyn
, E. Dentoni Litta
, A. Schulze
, C. Vrancken
, A. Opdebeeck
, J. Mitard
, R. Langer
, F. Holsteyns
, N. Waldron

K. Barla, V. De Heyn, D. Mocuta, N. Collaert

Interuniversitair Micro-Elektronica Centrum

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, I_on=500μA/μm at I_off=100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si_0.3Ge_0.7 SRB.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	191-194
Number of pages	4
ISBN (Electronic)	9781538642160
DOIs	https://doi.org/10.1109/VLSIT.2018.8510645
Publication status	Published - 25 Oct 2018
Externally published	Yes
Event	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2018-June
ISSN (Print)	0743-1562

Conference

Conference	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Country/Territory	United States
City	Honolulu
Period	18/06/18 → 22/06/18

Access to Document

10.1109/VLSIT.2018.8510645

Cite this

Capogreco, E., Witters, L., Arimura, H., Sebaai, F., Porret, C., Hikavyy, A., Loo, R., Milenin, A. P., Eneman, G., Favia, P., Bender, H., Wostyn, K., Litta, E. D., Schulze, A., Vrancken, C., Opdebeeck, A., Mitard, J., Langer, R., Holsteyns, F., ... Collaert, N. (2018). First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 191-194). Article 8510645 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510645

@inbook{2421aa15413e4fa7845001c29b3f4519,

title = "First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs",

abstract = "This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, Ion=500μA/μm at Ioff=100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si0.3Ge0.7 SRB.",

author = "E. Capogreco and L. Witters and H. Arimura and F. Sebaai and C. Porret and A. Hikavyy and R. Loo and Milenin, \{A. P.\} and G. Eneman and P. Favia and H. Bender and K. Wostyn and Litta, \{E. Dentoni\} and A. Schulze and C. Vrancken and A. Opdebeeck and J. Mitard and R. Langer and F. Holsteyns and N. Waldron and K. Barla and \{De Heyn\}, V. and D. Mocuta and N. Collaert",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 ; Conference date: 18-06-2018 Through 22-06-2018",

year = "2018",

month = oct,

day = "25",

doi = "10.1109/VLSIT.2018.8510645",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "191--194",

booktitle = "2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018",

address = "United States",

}

Capogreco, E, Witters, L, Arimura, H, Sebaai, F, Porret, C, Hikavyy, A, Loo, R, Milenin, AP, Eneman, G, Favia, P, Bender, H, Wostyn, K, Litta, ED, Schulze, A, Vrancken, C, Opdebeeck, A, Mitard, J, Langer, R, Holsteyns, F, Waldron, N, Barla, K, De Heyn, V, Mocuta, D & Collaert, N 2018, First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510645, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 191-194, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIT.2018.8510645

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs. / Capogreco, E.; Witters, L.; Arimura, H. et al.
2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 191-194 8510645 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

AU - Capogreco, E.

AU - Witters, L.

AU - Arimura, H.

AU - Sebaai, F.

AU - Porret, C.

AU - Hikavyy, A.

AU - Loo, R.

AU - Milenin, A. P.

AU - Eneman, G.

AU - Favia, P.

AU - Bender, H.

AU - Wostyn, K.

AU - Litta, E. Dentoni

AU - Schulze, A.

AU - Vrancken, C.

AU - Opdebeeck, A.

AU - Mitard, J.

AU - Langer, R.

AU - Holsteyns, F.

AU - Waldron, N.

AU - Barla, K.

AU - De Heyn, V.

AU - Mocuta, D.

AU - Collaert, N.

PY - 2018/10/25

Y1 - 2018/10/25

N2 - This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, Ion=500μA/μm at Ioff=100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si0.3Ge0.7 SRB.

AB - This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, Ion=500μA/μm at Ioff=100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si0.3Ge0.7 SRB.

UR - https://www.scopus.com/pages/publications/85055390398

U2 - 10.1109/VLSIT.2018.8510645

DO - 10.1109/VLSIT.2018.8510645

M3 - Chapter

AN - SCOPUS:85055390398

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 191

EP - 194

BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018

Y2 - 18 June 2018 through 22 June 2018

ER -

Capogreco E, Witters L, Arimura H, Sebaai F, Porret C, Hikavyy A et al. First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 191-194. 8510645. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2018.8510645

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this