First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs

E. Capogreco; L. Witters; H. Arimura; F. Sebaai; C. Porret; A. Hikavyy; R. Loo; A. P. Milenin; G. Eneman; P. Favia; H. Bender; K. Wostyn; E. Dentoni Litta; A. Schulze; C. Vrancken; A. Opdebeeck; J. Mitard; R. Langer; F. Holsteyns; N. Waldron; K. Barla; V. De Heyn; D. Mocuta; N. Collaert

doi:10.1109/TED.2018.2871595

First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs

E. Capogreco
, L. Witters
, H. Arimura
, F. Sebaai
, C. Porret
, A. Hikavyy
, R. Loo
, A. P. Milenin
, G. Eneman
, P. Favia
, H. Bender
, K. Wostyn
, E. Dentoni Litta
, A. Schulze
, C. Vrancken
, A. Opdebeeck
, J. Mitard
, R. Langer
, F. Holsteyns
, N. Waldron

K. Barla, V. De Heyn, D. Mocuta, N. Collaert

Interuniversitair Micro-Elektronica Centrum

Research output: Contribution to journal › Article › peer-review

Abstract

This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: The Q factor is increased to 25 as compared to our previous work, I_ON = 500 μA/μm at I_OFF = 100 nA/μm is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si_0.3Ge_0.7 SRB.

Original language	English
Article number	8489968
Pages (from-to)	5145-5150
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	65
Issue number	11
DOIs	https://doi.org/10.1109/TED.2018.2871595
Publication status	Published - Nov 2018
Externally published	Yes

Keywords

finFET
gate-all-around (GAA)
nanowire (NW)
strained germanium
strained relaxed buffer (SRB)

Access to Document

10.1109/TED.2018.2871595

Cite this

Capogreco, E., Witters, L., Arimura, H., Sebaai, F., Porret, C., Hikavyy, A., Loo, R., Milenin, A. P., Eneman, G., Favia, P., Bender, H., Wostyn, K., Dentoni Litta, E., Schulze, A., Vrancken, C., Opdebeeck, A., Mitard, J., Langer, R., Holsteyns, F., ... Collaert, N. (2018). First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs. IEEE Transactions on Electron Devices, 65(11), 5145-5150. Article 8489968. https://doi.org/10.1109/TED.2018.2871595

@article{9c14d86721de4fd4b0c05fbdd848a345,

title = "First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs",

abstract = "This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: The Q factor is increased to 25 as compared to our previous work, ION = 500 μA/μm at IOFF = 100 nA/μm is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB.",

keywords = "finFET, gate-all-around (GAA), nanowire (NW), strained germanium, strained relaxed buffer (SRB)",

author = "E. Capogreco and L. Witters and H. Arimura and F. Sebaai and C. Porret and A. Hikavyy and R. Loo and Milenin, \{A. P.\} and G. Eneman and P. Favia and H. Bender and K. Wostyn and \{Dentoni Litta\}, E. and A. Schulze and C. Vrancken and A. Opdebeeck and J. Mitard and R. Langer and F. Holsteyns and N. Waldron and K. Barla and \{De Heyn\}, V. and D. Mocuta and N. Collaert",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2018",

month = nov,

doi = "10.1109/TED.2018.2871595",

language = "English",

volume = "65",

pages = "5145--5150",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

Capogreco, E, Witters, L, Arimura, H, Sebaai, F, Porret, C, Hikavyy, A, Loo, R, Milenin, AP, Eneman, G, Favia, P, Bender, H, Wostyn, K, Dentoni Litta, E, Schulze, A, Vrancken, C, Opdebeeck, A, Mitard, J, Langer, R, Holsteyns, F, Waldron, N, Barla, K, De Heyn, V, Mocuta, D & Collaert, N 2018, 'First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs', IEEE Transactions on Electron Devices, vol. 65, no. 11, 8489968, pp. 5145-5150. https://doi.org/10.1109/TED.2018.2871595

TY - JOUR

T1 - First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs

AU - Capogreco, E.

AU - Witters, L.

AU - Arimura, H.

AU - Sebaai, F.

AU - Porret, C.

AU - Hikavyy, A.

AU - Loo, R.

AU - Milenin, A. P.

AU - Eneman, G.

AU - Favia, P.

AU - Bender, H.

AU - Wostyn, K.

AU - Dentoni Litta, E.

AU - Schulze, A.

AU - Vrancken, C.

AU - Opdebeeck, A.

AU - Mitard, J.

AU - Langer, R.

AU - Holsteyns, F.

AU - Waldron, N.

AU - Barla, K.

AU - De Heyn, V.

AU - Mocuta, D.

AU - Collaert, N.

PY - 2018/11

Y1 - 2018/11

N2 - This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: The Q factor is increased to 25 as compared to our previous work, ION = 500 μA/μm at IOFF = 100 nA/μm is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB.

AB - This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: The Q factor is increased to 25 as compared to our previous work, ION = 500 μA/μm at IOFF = 100 nA/μm is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB.

KW - finFET

KW - gate-all-around (GAA)

KW - nanowire (NW)

KW - strained germanium

KW - strained relaxed buffer (SRB)

UR - https://www.scopus.com/pages/publications/85054655529

U2 - 10.1109/TED.2018.2871595

DO - 10.1109/TED.2018.2871595

M3 - Article

AN - SCOPUS:85054655529

SN - 0018-9383

VL - 65

SP - 5145

EP - 5150

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 11

M1 - 8489968

ER -

First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this