First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

  • T. Mérelle
  • , G. Curatola
  • , A. Nackaerts
  • , N. Collaert
  • , M. J.H. Van Dal
  • , G. Doornbos
  • , T. S. Doorn
  • , P. Christie
  • , G. Vellianitis
  • , B. Duriez
  • , R. Duffy
  • , B. J. Pawlak
  • , F. C. Voogt
  • , R. Rooyackers
  • , L. Witters
  • , M. Jurczak
  • , R. J.P. Lander

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, β-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in β-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.

Original languageEnglish
Title of host publication2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States
Duration: 15 Dec 200817 Dec 2008

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2008 IEEE International Electron Devices Meeting, IEDM 2008
Country/TerritoryUnited States
CitySan Francisco, CA
Period15/12/0817/12/08

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