First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

T. Mérelle; G. Curatola; A. Nackaerts; N. Collaert; M. J.H. Van Dal; G. Doornbos; T. S. Doorn; P. Christie; G. Vellianitis; B. Duriez; R. Duffy; B. J. Pawlak; F. C. Voogt; R. Rooyackers; L. Witters; M. Jurczak; R. J.P. Lander

doi:10.1109/IEDM.2008.4796662

First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

T. Mérelle
, G. Curatola
, A. Nackaerts
, N. Collaert
, M. J.H. Van Dal
, G. Doornbos
, T. S. Doorn
, P. Christie
, G. Vellianitis
, B. Duriez
, R. Duffy
, B. J. Pawlak
, F. C. Voogt
, R. Rooyackers
, L. Witters
, M. Jurczak
, R. J.P. Lander

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

V_t-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, β-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in β-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.

Original language	English
Title of host publication	2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs	https://doi.org/10.1109/IEDM.2008.4796662
Publication status	Published - 2008
Externally published	Yes
Event	2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States Duration: 15 Dec 2008 → 17 Dec 2008

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2008 IEEE International Electron Devices Meeting, IEDM 2008
Country/Territory	United States
City	San Francisco, CA
Period	15/12/08 → 17/12/08

Access to Document

10.1109/IEDM.2008.4796662

Cite this

Mérelle, T., Curatola, G., Nackaerts, A., Collaert, N., Van Dal, M. J. H., Doornbos, G., Doorn, T. S., Christie, P., Vellianitis, G., Duriez, B., Duffy, R., Pawlak, B. J., Voogt, F. C., Rooyackers, R., Witters, L., Jurczak, M., & Lander, R. J. P. (2008). First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling. In 2008 IEEE International Electron Devices Meeting, IEDM 2008 Article 4796662 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2008.4796662

@inproceedings{738ce5843e2c45e3aa39b11d344f4801,

title = "First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling",

abstract = "Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, β-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in β-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.",

author = "T. M{\'e}relle and G. Curatola and A. Nackaerts and N. Collaert and \{Van Dal\}, \{M. J.H.\} and G. Doornbos and Doorn, \{T. S.\} and P. Christie and G. Vellianitis and B. Duriez and R. Duffy and Pawlak, \{B. J.\} and Voogt, \{F. C.\} and R. Rooyackers and L. Witters and M. Jurczak and Lander, \{R. J.P.\}",

year = "2008",

doi = "10.1109/IEDM.2008.4796662",

language = "English",

isbn = "9781424423781",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

booktitle = "2008 IEEE International Electron Devices Meeting, IEDM 2008",

note = "2008 IEEE International Electron Devices Meeting, IEDM 2008 ; Conference date: 15-12-2008 Through 17-12-2008",

}

Mérelle, T, Curatola, G, Nackaerts, A, Collaert, N, Van Dal, MJH, Doornbos, G, Doorn, TS, Christie, P, Vellianitis, G, Duriez, B, Duffy, R, Pawlak, BJ, Voogt, FC, Rooyackers, R, Witters, L, Jurczak, M & Lander, RJP 2008, First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling. in 2008 IEEE International Electron Devices Meeting, IEDM 2008., 4796662, Technical Digest - International Electron Devices Meeting, IEDM, 2008 IEEE International Electron Devices Meeting, IEDM 2008, San Francisco, CA, United States, 15/12/08. https://doi.org/10.1109/IEDM.2008.4796662

First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling. / Mérelle, T.; Curatola, G.; Nackaerts, A. et al.
2008 IEEE International Electron Devices Meeting, IEDM 2008. 2008. 4796662 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

AU - Mérelle, T.

AU - Curatola, G.

AU - Nackaerts, A.

AU - Collaert, N.

AU - Van Dal, M. J.H.

AU - Doornbos, G.

AU - Doorn, T. S.

AU - Christie, P.

AU - Vellianitis, G.

AU - Duriez, B.

AU - Duffy, R.

AU - Pawlak, B. J.

AU - Voogt, F. C.

AU - Rooyackers, R.

AU - Witters, L.

AU - Jurczak, M.

AU - Lander, R. J.P.

PY - 2008

Y1 - 2008

N2 - Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, β-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in β-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.

AB - Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, β-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in β-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.

UR - https://www.scopus.com/pages/publications/64549103332

U2 - 10.1109/IEDM.2008.4796662

DO - 10.1109/IEDM.2008.4796662

M3 - Conference proceeding

AN - SCOPUS:64549103332

SN - 9781424423781

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2008 IEEE International Electron Devices Meeting, IEDM 2008

T2 - 2008 IEEE International Electron Devices Meeting, IEDM 2008

Y2 - 15 December 2008 through 17 December 2008

ER -

First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

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