FPGA acceleration of the tate pairing in characteristic 2

Robert Ronan; Colm Ó Héigeartaigh; Colin Murphy; Michael Scott; Tim Kerins

doi:10.1109/FPT.2006.270314

FPGA acceleration of the tate pairing in characteristic 2

Robert Ronan
, Colm Ó Héigeartaigh
, Colin Murphy
, Michael Scott
, Tim Kerins

School of Engineering and Architecture

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

This paper presents a dedicated hardware implementation of the cryptographic Tate pairing on an elliptic curve of characteristic 2 using the η_T method. Efficient techniques for pairing computation are discussed and optimised hardware architectures are presented. A hardware pipelining scheme is described, which provides a dramatic reduction in pairing computation time. A cryptographic processor for computation of the bilinear pairing is presented and implemented on an FPGA. It is demonstrated that an FPGA forms an ideal basis for pairing processor implementation due to ease of reconfigurability and the opportunity for rapid prototyping. Implementation results are provided for pairing calculation on an FPGA over the base field double-struck F sign₂313.

Original language	English
Title of host publication	Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
Pages	213-220
Number of pages	8
DOIs	https://doi.org/10.1109/FPT.2006.270314
Publication status	Published - 2006
Event	2006 IEEE International Conference on Field Programmable Technology, FPT 2006 - Bangkok, Thailand Duration: 13 Dec 2006 → 15 Dec 2006

Publication series

Name	Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Conference

Conference	2006 IEEE International Conference on Field Programmable Technology, FPT 2006
Country/Territory	Thailand
City	Bangkok
Period	13/12/06 → 15/12/06

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

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10.1109/FPT.2006.270314

Cite this

Ronan, R., Héigeartaigh, C. Ó., Murphy, C., Scott, M., & Kerins, T. (2006). FPGA acceleration of the tate pairing in characteristic 2. In Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006 (pp. 213-220). Article 4042436 (Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006). https://doi.org/10.1109/FPT.2006.270314

@inproceedings{f87f76ec98124653b141cbec4b036d7c,

title = "FPGA acceleration of the tate pairing in characteristic 2",

abstract = "This paper presents a dedicated hardware implementation of the cryptographic Tate pairing on an elliptic curve of characteristic 2 using the ηT method. Efficient techniques for pairing computation are discussed and optimised hardware architectures are presented. A hardware pipelining scheme is described, which provides a dramatic reduction in pairing computation time. A cryptographic processor for computation of the bilinear pairing is presented and implemented on an FPGA. It is demonstrated that an FPGA forms an ideal basis for pairing processor implementation due to ease of reconfigurability and the opportunity for rapid prototyping. Implementation results are provided for pairing calculation on an FPGA over the base field double-struck F sign2313.",

author = "Robert Ronan and H{\'e}igeartaigh, \{Colm {\'O}\} and Colin Murphy and Michael Scott and Tim Kerins",

year = "2006",

doi = "10.1109/FPT.2006.270314",

language = "English",

isbn = "0780397282",

series = "Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006",

pages = "213--220",

booktitle = "Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006",

note = "2006 IEEE International Conference on Field Programmable Technology, FPT 2006 ; Conference date: 13-12-2006 Through 15-12-2006",

}

Ronan, R, Héigeartaigh, CÓ, Murphy, C, Scott, M & Kerins, T 2006, FPGA acceleration of the tate pairing in characteristic 2. in Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006., 4042436, Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, pp. 213-220, 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, 13/12/06. https://doi.org/10.1109/FPT.2006.270314

FPGA acceleration of the tate pairing in characteristic 2. / Ronan, Robert; Héigeartaigh, Colm Ó; Murphy, Colin et al.
Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006. 2006. p. 213-220 4042436 (Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - FPGA acceleration of the tate pairing in characteristic 2

AU - Ronan, Robert

AU - Héigeartaigh, Colm Ó

AU - Murphy, Colin

AU - Scott, Michael

AU - Kerins, Tim

PY - 2006

Y1 - 2006

N2 - This paper presents a dedicated hardware implementation of the cryptographic Tate pairing on an elliptic curve of characteristic 2 using the ηT method. Efficient techniques for pairing computation are discussed and optimised hardware architectures are presented. A hardware pipelining scheme is described, which provides a dramatic reduction in pairing computation time. A cryptographic processor for computation of the bilinear pairing is presented and implemented on an FPGA. It is demonstrated that an FPGA forms an ideal basis for pairing processor implementation due to ease of reconfigurability and the opportunity for rapid prototyping. Implementation results are provided for pairing calculation on an FPGA over the base field double-struck F sign2313.

AB - This paper presents a dedicated hardware implementation of the cryptographic Tate pairing on an elliptic curve of characteristic 2 using the ηT method. Efficient techniques for pairing computation are discussed and optimised hardware architectures are presented. A hardware pipelining scheme is described, which provides a dramatic reduction in pairing computation time. A cryptographic processor for computation of the bilinear pairing is presented and implemented on an FPGA. It is demonstrated that an FPGA forms an ideal basis for pairing processor implementation due to ease of reconfigurability and the opportunity for rapid prototyping. Implementation results are provided for pairing calculation on an FPGA over the base field double-struck F sign2313.

UR - https://www.scopus.com/pages/publications/43749084159

U2 - 10.1109/FPT.2006.270314

DO - 10.1109/FPT.2006.270314

M3 - Conference proceeding

AN - SCOPUS:43749084159

SN - 0780397282

SN - 9780780397286

T3 - Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

SP - 213

EP - 220

BT - Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

T2 - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Y2 - 13 December 2006 through 15 December 2006

ER -

FPGA acceleration of the tate pairing in characteristic 2

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