TY - CHAP
T1 - FPGA design trade-offs for solving the key equation in reed-solomon decoding
AU - Popovici, Emanuel M.
AU - Fitzpatrick, Patrick
AU - Murphy, Colin C.
N1 - Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 1999.
PY - 1999
Y1 - 1999
N2 - Reed-Solomon codes are widely used in communications as well as in data storage for the correction of errors due to channel noise. In this paper we present a comparison between implementations of the Berlekamp-Massey algorithm and the Fitzpatrick algorithm. Both algorithms were synthesised and implemented on an FPGA and compared in terms of area, speed and routability. The modules can be used as part of a core-based design for Reed-Solomon decoders.
AB - Reed-Solomon codes are widely used in communications as well as in data storage for the correction of errors due to channel noise. In this paper we present a comparison between implementations of the Berlekamp-Massey algorithm and the Fitzpatrick algorithm. Both algorithms were synthesised and implemented on an FPGA and compared in terms of area, speed and routability. The modules can be used as part of a core-based design for Reed-Solomon decoders.
UR - https://www.scopus.com/pages/publications/84956853160
U2 - 10.1007/978-3-540-48302-1_37
DO - 10.1007/978-3-540-48302-1_37
M3 - Chapter
AN - SCOPUS:84956853160
SN - 3540664572
SN - 9783540664574
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 353
EP - 358
BT - Field Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings
A2 - Lysaght, Patrick
A2 - Irvine, James
A2 - Hartenstein, Reiner W.
PB - Springer Verlag
T2 - 9th International Workshop on Field Programmable Logic and Applications, FPL 1999
Y2 - 30 August 1999 through 1 September 1999
ER -