FPGA implementation of a GF(24M) multiplier for use in pairing based cryptosystems

Maurice Keller; Tim Kerins; William Marnane

doi:10.1109/FPL.2005.1515793

FPGA implementation of a GF(2^4M) multiplier for use in pairing based cryptosystems

Maurice Keller
, Tim Kerins
, William Marnane

University College Cork

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

In this paper an architecture for GF(2^4m) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tate pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.

Original language	English
Title of host publication	Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
Pages	594-597
Number of pages	4
DOIs	https://doi.org/10.1109/FPL.2005.1515793
Publication status	Published - 2005
Event	2005 International Conference on Field Programmable Logic and Applications, FPL - Tampere, Finland Duration: 24 Aug 2005 → 26 Aug 2005

Publication series

Name	Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
Volume	2005

Conference

Conference	2005 International Conference on Field Programmable Logic and Applications, FPL
Country/Territory	Finland
City	Tampere
Period	24/08/05 → 26/08/05

Access to Document

10.1109/FPL.2005.1515793

Cite this

Keller, M., Kerins, T., & Marnane, W. (2005). FPGA implementation of a GF(2^4M) multiplier for use in pairing based cryptosystems. In Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL (pp. 594-597). Article 1515793 (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; Vol. 2005). https://doi.org/10.1109/FPL.2005.1515793

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title = "FPGA implementation of a GF(24M) multiplier for use in pairing based cryptosystems",

abstract = "In this paper an architecture for GF(24m) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tate pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.",

author = "Maurice Keller and Tim Kerins and William Marnane",

year = "2005",

doi = "10.1109/FPL.2005.1515793",

language = "English",

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series = "Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL",

pages = "594--597",

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note = "2005 International Conference on Field Programmable Logic and Applications, FPL ; Conference date: 24-08-2005 Through 26-08-2005",

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Keller, M, Kerins, T & Marnane, W 2005, FPGA implementation of a GF(2^4M) multiplier for use in pairing based cryptosystems. in Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL., 1515793, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL, vol. 2005, pp. 594-597, 2005 International Conference on Field Programmable Logic and Applications, FPL, Tampere, Finland, 24/08/05. https://doi.org/10.1109/FPL.2005.1515793

FPGA implementation of a GF(2^4M) multiplier for use in pairing based cryptosystems. / Keller, Maurice; Kerins, Tim; Marnane, William.
Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. 2005. p. 594-597 1515793 (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

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