FPGA implementation of a GF(2m) tate pairing architecture

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

This paper presents a hardware implementation of a dual mode Tate pairing/elliptic curve processor over fields of characteristic 2. The architecture can be reconfigured for different underlying field sizes and hence can support different security levels. The processor also performs elliptic curve point scalar multiplication. The performance of the architecture implemented on an FPGA is evaluated for various security levels.

Original languageEnglish
Title of host publicationReconfigurable Computing
Subtitle of host publicationArchitectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers
PublisherSpringer Verlag
Pages358-369
Number of pages12
ISBN (Print)9783540367086
DOIs
Publication statusPublished - 2006
Event2nd International Workshop on Applied Reconfigurable Computing, ARC 2006 - Delft, United States
Duration: 1 Mar 20063 Mar 2006

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3985 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference2nd International Workshop on Applied Reconfigurable Computing, ARC 2006
Country/TerritoryUnited States
CityDelft
Period1/03/063/03/06

Fingerprint

Dive into the research topics of 'FPGA implementation of a GF(2m) tate pairing architecture'. Together they form a unique fingerprint.

Cite this