FPGA implementation of an elliptic curve processor using the GLV method

Mark Hamilton; William P. Marnane

doi:10.1109/ReConFig.2009.66

FPGA implementation of an elliptic curve processor using the GLV method

Mark Hamilton
, William P. Marnane

University College Cork

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

This paper outlines a FPGA implementation of an elliptic curve processor that utilises the GLV method. The GLV method has been shown to be able to speed up computationally expensive point multiplication operations. We also present an implementation of a Hiasat multiplier which can be used with special moduli to further speed up point multiplications. The Hiasat multiplier takes advantage of fast reduction techniques that can be applied to Mersenne primes. The results are then compared with standard multiplication algorithms.

Original language	English
Title of host publication	ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs
Pages	249-254
Number of pages	6
DOIs	https://doi.org/10.1109/ReConFig.2009.66
Publication status	Published - 2009
Event	2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09 - Cancun, Mexico Duration: 9 Dec 2009 → 11 Dec 2009

Publication series

Name	ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs

Conference

Conference	2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09
Country/Territory	Mexico
City	Cancun
Period	9/12/09 → 11/12/09

Keywords

Elliptic curve processor
FPGA
GLV method
Hiasat Multiplier
Mersenne prime

Access to Document

10.1109/ReConFig.2009.66

Cite this

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title = "FPGA implementation of an elliptic curve processor using the GLV method",

abstract = "This paper outlines a FPGA implementation of an elliptic curve processor that utilises the GLV method. The GLV method has been shown to be able to speed up computationally expensive point multiplication operations. We also present an implementation of a Hiasat multiplier which can be used with special moduli to further speed up point multiplications. The Hiasat multiplier takes advantage of fast reduction techniques that can be applied to Mersenne primes. The results are then compared with standard multiplication algorithms.",

keywords = "Elliptic curve processor, FPGA, GLV method, Hiasat Multiplier, Mersenne prime",

author = "Mark Hamilton and Marnane, \{William P.\}",

year = "2009",

doi = "10.1109/ReConFig.2009.66",

language = "English",

isbn = "9780769539171",

series = "ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs",

pages = "249--254",

booktitle = "ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs",

note = "2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09 ; Conference date: 09-12-2009 Through 11-12-2009",

}

Hamilton, M & Marnane, WP 2009, FPGA implementation of an elliptic curve processor using the GLV method. in ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs., 5382060, ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs, pp. 249-254, 2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09, Cancun, Mexico, 9/12/09. https://doi.org/10.1109/ReConFig.2009.66

FPGA implementation of an elliptic curve processor using the GLV method. / Hamilton, Mark; Marnane, William P.
ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs. 2009. p. 249-254 5382060 (ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

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AB - This paper outlines a FPGA implementation of an elliptic curve processor that utilises the GLV method. The GLV method has been shown to be able to speed up computationally expensive point multiplication operations. We also present an implementation of a Hiasat multiplier which can be used with special moduli to further speed up point multiplications. The Hiasat multiplier takes advantage of fast reduction techniques that can be applied to Mersenne primes. The results are then compared with standard multiplication algorithms.

KW - Elliptic curve processor

KW - FPGA

KW - GLV method

KW - Hiasat Multiplier

KW - Mersenne prime

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BT - ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs

T2 - 2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09

Y2 - 9 December 2009 through 11 December 2009

ER -

FPGA implementation of an elliptic curve processor using the GLV method

Abstract

Publication series

Conference

Keywords

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