FPGA implementations of LDPC over GF(2m) decoders

Christian Spagnol; William Marnane; Emanuel Popovici

doi:10.1109/SIPS.2007.4387557

FPGA implementations of LDPC over GF(2^m) decoders

Christian Spagnol
, William Marnane
, Emanuel Popovici

University College Cork

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

Low Density Parity Check (LDPC) codes over GF(2^m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2^m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there is a substantial lack of hardware implementations for LDPC over GF(2 ^m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2^m). The results prove that the implementation of LDPC over GF(2^m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2 ^m) LDPC codes.

Original language	English
Title of host publication	2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings
Pages	273-278
Number of pages	6
DOIs	https://doi.org/10.1109/SIPS.2007.4387557
Publication status	Published - 2007
Event	2007 IEEE Workshop on Signal Processing Systems, SiPS 2007 - Shanghai, China Duration: 17 Oct 2007 → 19 Oct 2007

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)	1520-6130

Conference

Conference	2007 IEEE Workshop on Signal Processing Systems, SiPS 2007
Country/Territory	China
City	Shanghai
Period	17/10/07 → 19/10/07

Keywords

Block codes
Decoding
FPGA
Galois fields

Access to Document

10.1109/SIPS.2007.4387557

Cite this

@inbook{7dd21dcbe1124722aa76697592114b49,

title = "FPGA implementations of LDPC over GF(2m) decoders",

abstract = "Low Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there is a substantial lack of hardware implementations for LDPC over GF(2 m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2 m) LDPC codes.",

keywords = "Block codes, Decoding, FPGA, Galois fields",

author = "Christian Spagnol and William Marnane and Emanuel Popovici",

year = "2007",

doi = "10.1109/SIPS.2007.4387557",

language = "English",

isbn = "1424412226",

series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

pages = "273--278",

booktitle = "2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings",

note = "2007 IEEE Workshop on Signal Processing Systems, SiPS 2007 ; Conference date: 17-10-2007 Through 19-10-2007",

}

Spagnol, C, Marnane, W & Popovici, E 2007, FPGA implementations of LDPC over GF(2^m) decoders. in 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings., 4387557, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, pp. 273-278, 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Shanghai, China, 17/10/07. https://doi.org/10.1109/SIPS.2007.4387557

FPGA implementations of LDPC over GF(2^m) decoders. / Spagnol, Christian; Marnane, William ; Popovici, Emanuel.
2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings. 2007. p. 273-278 4387557 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - FPGA implementations of LDPC over GF(2m) decoders

AU - Spagnol, Christian

AU - Marnane, William

AU - Popovici, Emanuel

PY - 2007

Y1 - 2007

N2 - Low Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there is a substantial lack of hardware implementations for LDPC over GF(2 m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2 m) LDPC codes.

AB - Low Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there is a substantial lack of hardware implementations for LDPC over GF(2 m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2 m) LDPC codes.

KW - Block codes

KW - Decoding

KW - FPGA

KW - Galois fields

UR - https://www.scopus.com/pages/publications/47949130356

U2 - 10.1109/SIPS.2007.4387557

DO - 10.1109/SIPS.2007.4387557

M3 - Chapter

AN - SCOPUS:47949130356

SN - 1424412226

SN - 9781424412228

T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

SP - 273

EP - 278

BT - 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings

T2 - 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007

Y2 - 17 October 2007 through 19 October 2007

ER -