FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash

Brian Baldwin; Andrew Byrne; Mark Hamilton; Neil Hanley; Robert P. McEvoy; Weibo Pan; William P. Marnane

doi:10.1109/DSD.2009.162

FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash

Brian Baldwin
, Andrew Byrne
, Mark Hamilton
, Neil Hanley
, Robert P. McEvoy
, Weibo Pan
, William P. Marnane

University College Cork

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

Hash functions are widely used in, and form an important part of many cryptographic protocols. Currently, a public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware will form one of the evaluation criteria. In this paper, we focus on five of these candidate algorithms, namely CubeHash, Grøstl, LANE, Shabal and Spectral Hash. Using Xilinx Spartan-3 and Virtex-5 FPGAs, we present architectures for each of these hash functions, and explore area-speed trade-offs in each design. The efficiency of various architectures for the five hash functions is compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first such comparison of these SHA-3 candidates in the literature.

Original language	English
Title of host publication	12th Euromicro Conference on Digital System Design
Subtitle of host publication	Architectures, Methods and Tools, DSD 2009
Pages	783-790
Number of pages	8
DOIs	https://doi.org/10.1109/DSD.2009.162
Publication status	Published - 2009
Event	12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 - Patras, Greece Duration: 27 Aug 2009 → 29 Aug 2009

Publication series

Name	12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Conference

Conference	12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009
Country/Territory	Greece
City	Patras
Period	27/08/09 → 29/08/09

Access to Document

10.1109/DSD.2009.162

Cite this

Baldwin, B., Byrne, A., Hamilton, M., Hanley, N., McEvoy, R. P., Pan, W., & Marnane, W. P. (2009). FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash. In 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 (pp. 783-790). Article 5350099 (12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009). https://doi.org/10.1109/DSD.2009.162

@inbook{51c72ded50ab4e449310513f7ce5515a,

title = "FPGA implementations of SHA-3 candidates: CubeHash, Gr{\o}stl, Lane, Shabal and Spectral Hash",

abstract = "Hash functions are widely used in, and form an important part of many cryptographic protocols. Currently, a public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware will form one of the evaluation criteria. In this paper, we focus on five of these candidate algorithms, namely CubeHash, Gr{\o}stl, LANE, Shabal and Spectral Hash. Using Xilinx Spartan-3 and Virtex-5 FPGAs, we present architectures for each of these hash functions, and explore area-speed trade-offs in each design. The efficiency of various architectures for the five hash functions is compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first such comparison of these SHA-3 candidates in the literature.",

author = "Brian Baldwin and Andrew Byrne and Mark Hamilton and Neil Hanley and McEvoy, \{Robert P.\} and Weibo Pan and Marnane, \{William P.\}",

year = "2009",

doi = "10.1109/DSD.2009.162",

language = "English",

isbn = "9780769537825",

series = "12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009",

pages = "783--790",

booktitle = "12th Euromicro Conference on Digital System Design",

note = "12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 ; Conference date: 27-08-2009 Through 29-08-2009",

}

Baldwin, B, Byrne, A, Hamilton, M, Hanley, N, McEvoy, RP, Pan, W & Marnane, WP 2009, FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash. in 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009., 5350099, 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009, pp. 783-790, 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009, Patras, Greece, 27/08/09. https://doi.org/10.1109/DSD.2009.162

FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash. / Baldwin, Brian; Byrne, Andrew; Hamilton, Mark et al.
12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009. 2009. p. 783-790 5350099 (12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - FPGA implementations of SHA-3 candidates

T2 - 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

AU - Baldwin, Brian

AU - Byrne, Andrew

AU - Hamilton, Mark

AU - Hanley, Neil

AU - McEvoy, Robert P.

AU - Pan, Weibo

AU - Marnane, William P.

PY - 2009

Y1 - 2009

N2 - Hash functions are widely used in, and form an important part of many cryptographic protocols. Currently, a public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware will form one of the evaluation criteria. In this paper, we focus on five of these candidate algorithms, namely CubeHash, Grøstl, LANE, Shabal and Spectral Hash. Using Xilinx Spartan-3 and Virtex-5 FPGAs, we present architectures for each of these hash functions, and explore area-speed trade-offs in each design. The efficiency of various architectures for the five hash functions is compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first such comparison of these SHA-3 candidates in the literature.

AB - Hash functions are widely used in, and form an important part of many cryptographic protocols. Currently, a public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware will form one of the evaluation criteria. In this paper, we focus on five of these candidate algorithms, namely CubeHash, Grøstl, LANE, Shabal and Spectral Hash. Using Xilinx Spartan-3 and Virtex-5 FPGAs, we present architectures for each of these hash functions, and explore area-speed trade-offs in each design. The efficiency of various architectures for the five hash functions is compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first such comparison of these SHA-3 candidates in the literature.

UR - https://www.scopus.com/pages/publications/74549151790

U2 - 10.1109/DSD.2009.162

DO - 10.1109/DSD.2009.162

M3 - Chapter

AN - SCOPUS:74549151790

SN - 9780769537825

T3 - 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

SP - 783

EP - 790

BT - 12th Euromicro Conference on Digital System Design

Y2 - 27 August 2009 through 29 August 2009

ER -

Baldwin B, Byrne A, Hamilton M, Hanley N, McEvoy RP, Pan W et al. FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash. In 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009. 2009. p. 783-790. 5350099. (12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009). doi: 10.1109/DSD.2009.162

FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this