TY - GEN
T1 - FPGA implementations of the round two SHA-3 candidates
AU - Baldwin, Brian
AU - Byrnet, Andrew
AU - Lu, Liang
AU - Hamilton, Mark
AU - Hanley, Neil
AU - O'Neill, Maire
AU - Marnane, William P.
PY - 2010
Y1 - 2010
N2 - The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants. In order to determine their computational efficiency, an important aspect in NIST's round two evaluation criteria, this paper gives an area/speed comparison of each design both with and without a hardware interface, thereby giving an overall impression of their performance in resource constrained and resource abundant environments. The implementation results are provided for a Virtex-5 FPGA device. The efficiency of the architectures for the hash functions are compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first work to date to present hardware designs which test for all message digest sizes (224, 256, 384, 512), and also the only work to include the padding as part of the hardware for the SHA-3 hash functions.
AB - The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants. In order to determine their computational efficiency, an important aspect in NIST's round two evaluation criteria, this paper gives an area/speed comparison of each design both with and without a hardware interface, thereby giving an overall impression of their performance in resource constrained and resource abundant environments. The implementation results are provided for a Virtex-5 FPGA device. The efficiency of the architectures for the hash functions are compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first work to date to present hardware designs which test for all message digest sizes (224, 256, 384, 512), and also the only work to include the padding as part of the hardware for the SHA-3 hash functions.
UR - https://www.scopus.com/pages/publications/79951752768
U2 - 10.1109/FPL.2010.84
DO - 10.1109/FPL.2010.84
M3 - Conference proceeding
AN - SCOPUS:79951752768
SN - 9780769541792
T3 - Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010
SP - 400
EP - 407
BT - Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010
T2 - 20th International Conference on Field Programmable Logic and Applications, FPL 2010
Y2 - 31 August 2010 through 2 September 2010
ER -