Fully CMOS-compatible top-down fabrication of sub-50 nm silicon nanowire sensing devices

This article reports the fabrication of sub-50 nm field effect transistor (FET)-type silicon (Si) nanowire (Si NW) chemical and biological sensing devices with a junctionless architecture, as well as on the initial characterisation of their electrical and sensing performance. The devices were fabricated using a fully complementary metal-oxide-semiconductor (CMOS)-compatible top-down process on silicon-on-insulator (SOI) wafers. The fabrication process was mainly based on high-resolution electron beam lithography (EBL) and reactive ion etching (RIE) but also included photolithography (mix-and-match lithography), thin film deposition by electron beam evaporation, lift-off, thermal annealing and wet etching. The sensing performance of a matrix of nanowire devices, i.e. containing 1, 3 and 20 NWs with lengths of 0.5, 1 and 10 μm was examined. Each element of the matrix also contained five devices with different NW widths: 10, 20, 30, and 50 nm and 5 μm (a Si belt reference device). Electrical characterisation of the devices showed excellent performance as backgated junctionless nanowire transistors (JNTs): high on-currents in the range of 1-10 μA and high ratios between the on-state and off-state currents (I _on/I_off) of 6-7 orders of magnitude. In addition, the results of ionic strength sensing experiments demonstrate the very good sensing capabilities of these devices. To the best of our knowledge, these nanowire sensors are among the smallest top-down fabricated Si NW devices reported to date.