Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

N. Waldron; S. Sioncke; J. Franco; L. Nyns; A. Vais; X. Zhou; H. C. Lin; G. Boccardi; J. W. Maes; Q. Xie; M. Givens; F. Tang; X. Jiang; E. Chiu; A. Opdebeeck; C. Merckling; F. Sebaai; D. Van Dorp; L. Teugels; A. Sibaja Hernandez; K. De Meyer; K. Barla; N. Collaert; Y. V. Thean

doi:10.1109/IEDM.2015.7409805

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

N. Waldron
, S. Sioncke
, J. Franco
, L. Nyns
, A. Vais
, X. Zhou
, H. C. Lin
, G. Boccardi
, J. W. Maes
, Q. Xie
, M. Givens
, F. Tang
, X. Jiang
, E. Chiu
, A. Opdebeeck
, C. Merckling
, F. Sebaai
, D. Van Dorp
, L. Teugels
, A. Sibaja Hernandez

K. De Meyer, K. Barla, N. Collaert, Y. V. Thean

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

Original language	English
Title of host publication	2015 IEEE International Electron Devices Meeting, IEDM 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	3111-3114
Number of pages	4
ISBN (Electronic)	9781467398930
DOIs	https://doi.org/10.1109/IEDM.2015.7409805
Publication status	Published - 16 Feb 2015
Externally published	Yes
Event	61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States Duration: 7 Dec 2015 → 9 Dec 2015

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2016-February
ISSN (Print)	0163-1918

Conference

Conference	61st IEEE International Electron Devices Meeting, IEDM 2015
Country/Territory	United States
City	Washington
Period	7/12/15 → 9/12/15

Access to Document

10.1109/IEDM.2015.7409805

Cite this

Waldron, N., Sioncke, S., Franco, J., Nyns, L., Vais, A., Zhou, X., Lin, H. C., Boccardi, G., Maes, J. W., Xie, Q., Givens, M., Tang, F., Jiang, X., Chiu, E., Opdebeeck, A., Merckling, C., Sebaai, F., Van Dorp, D., Teugels, L., ... Thean, Y. V. (2015). Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow. In 2015 IEEE International Electron Devices Meeting, IEDM 2015 (pp. 3111-3114). Article 7409805 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409805

Waldron, N. ; Sioncke, S. ; Franco, J. et al. / Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow. 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 3111-3114 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{7a21b4c09dd54b72a34262f893fe9aad,

title = "Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow",

abstract = "We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22\% for a 400 °C anneal.",

author = "N. Waldron and S. Sioncke and J. Franco and L. Nyns and A. Vais and X. Zhou and Lin, \{H. C.\} and G. Boccardi and Maes, \{J. W.\} and Q. Xie and M. Givens and F. Tang and X. Jiang and E. Chiu and A. Opdebeeck and C. Merckling and F. Sebaai and \{Van Dorp\}, D. and L. Teugels and Hernandez, \{A. Sibaja\} and \{De Meyer\}, K. and K. Barla and N. Collaert and Thean, \{Y. V.\}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 61st IEEE International Electron Devices Meeting, IEDM 2015 ; Conference date: 07-12-2015 Through 09-12-2015",

year = "2015",

month = feb,

day = "16",

doi = "10.1109/IEDM.2015.7409805",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "3111--3114",

booktitle = "2015 IEEE International Electron Devices Meeting, IEDM 2015",

address = "United States",

}

Waldron, N, Sioncke, S, Franco, J, Nyns, L, Vais, A, Zhou, X, Lin, HC, Boccardi, G, Maes, JW, Xie, Q, Givens, M, Tang, F, Jiang, X, Chiu, E, Opdebeeck, A, Merckling, C, Sebaai, F, Van Dorp, D, Teugels, L, Hernandez, AS, De Meyer, K, Barla, K, Collaert, N & Thean, YV 2015, Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow. in 2015 IEEE International Electron Devices Meeting, IEDM 2015., 7409805, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2016-February, Institute of Electrical and Electronics Engineers Inc., pp. 3111-3114, 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, United States, 7/12/15. https://doi.org/10.1109/IEDM.2015.7409805

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow. / Waldron, N.; Sioncke, S.; Franco, J. et al.
2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 3111-3114 7409805 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

AU - Waldron, N.

AU - Sioncke, S.

AU - Franco, J.

AU - Nyns, L.

AU - Vais, A.

AU - Zhou, X.

AU - Lin, H. C.

AU - Boccardi, G.

AU - Maes, J. W.

AU - Xie, Q.

AU - Givens, M.

AU - Tang, F.

AU - Jiang, X.

AU - Chiu, E.

AU - Opdebeeck, A.

AU - Merckling, C.

AU - Sebaai, F.

AU - Van Dorp, D.

AU - Teugels, L.

AU - Hernandez, A. Sibaja

AU - De Meyer, K.

AU - Barla, K.

AU - Collaert, N.

AU - Thean, Y. V.

PY - 2015/2/16

Y1 - 2015/2/16

N2 - We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

AB - We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

UR - https://www.scopus.com/pages/publications/84964033747

U2 - 10.1109/IEDM.2015.7409805

DO - 10.1109/IEDM.2015.7409805

M3 - Conference proceeding

AN - SCOPUS:84964033747

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 3111

EP - 3114

BT - 2015 IEEE International Electron Devices Meeting, IEDM 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 61st IEEE International Electron Devices Meeting, IEDM 2015

Y2 - 7 December 2015 through 9 December 2015

ER -

Waldron N, Sioncke S, Franco J, Nyns L, Vais A, Zhou X et al. Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow. In 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 3111-3114. 7409805. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2015.7409805

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

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