Gatestacks for scalable high-performance FinFETs

G. Vellianitis; M. J.H. Van Dal; L. Witters; G. Curatola; G. Doornbos; N. Collaert; C. Jonville; C. Torregiani; L. S. Lai; J. Petry; B. J. Pawlak; R. Duffy; M. Demand; S. Beckx; S. Mertens; A. Delabie; T. Vandeweyer; C. Delvaux; F. Leys; A. Hikavyy; R. Rooyackers; M. Kaiser; R. Gr Weemaes; F. Voogt; H. Roberts; D. Donnet; S. Biesemans; M. Jurczak; R. J.P. Lander

doi:10.1109/IEDM.2007.4419037

Gatestacks for scalable high-performance FinFETs

G. Vellianitis
, M. J.H. Van Dal
, L. Witters
, G. Curatola
, G. Doornbos
, N. Collaert
, C. Jonville
, C. Torregiani
, L. S. Lai
, J. Petry
, B. J. Pawlak
, R. Duffy
, M. Demand
, S. Beckx
, S. Mertens
, A. Delabie
, T. Vandeweyer
, C. Delvaux
, F. Leys
, A. Hikavyy

R. Rooyackers, M. Kaiser, R. Gr Weemaes, F. Voogt, H. Roberts, D. Donnet, S. Biesemans, M. Jurczak, R. J.P. Lander

Research output: Contribution to journal › Article › peer-review

Abstract

Excellent performance (995μA/μm at I_off=94nA/μm and V_dd=1V) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193nm immersion lithography and dry etch. PVD TiN electrodes on HfSiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage V_T variability is shown to explain this dependence upon fin width and gate length.

Original language	English
Article number	4419037
Pages (from-to)	681-684
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2007.4419037
Publication status	Published - 2007
Externally published	Yes
Event	2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States Duration: 10 Dec 2007 → 12 Dec 2007

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Vellianitis, G., Van Dal, M. J. H., Witters, L., Curatola, G., Doornbos, G., Collaert, N., Jonville, C., Torregiani, C., Lai, L. S., Petry, J., Pawlak, B. J., Duffy, R., Demand, M., Beckx, S., Mertens, S., Delabie, A., Vandeweyer, T., Delvaux, C., Leys, F., ... Lander, R. J. P. (2007). Gatestacks for scalable high-performance FinFETs. Technical Digest - International Electron Devices Meeting, 681-684. Article 4419037. https://doi.org/10.1109/IEDM.2007.4419037

@article{1369151df43b416cb2dd7fff10b8f597,

title = "Gatestacks for scalable high-performance FinFETs",

abstract = "Excellent performance (995μA/μm at Ioff=94nA/μm and Vdd=1V) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193nm immersion lithography and dry etch. PVD TiN electrodes on HfSiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage VT variability is shown to explain this dependence upon fin width and gate length.",

author = "G. Vellianitis and \{Van Dal\}, \{M. J.H.\} and L. Witters and G. Curatola and G. Doornbos and N. Collaert and C. Jonville and C. Torregiani and Lai, \{L. S.\} and J. Petry and Pawlak, \{B. J.\} and R. Duffy and M. Demand and S. Beckx and S. Mertens and A. Delabie and T. Vandeweyer and C. Delvaux and F. Leys and A. Hikavyy and R. Rooyackers and M. Kaiser and Weemaes, \{R. Gr\} and F. Voogt and H. Roberts and D. Donnet and S. Biesemans and M. Jurczak and Lander, \{R. J.P.\}",

year = "2007",

doi = "10.1109/IEDM.2007.4419037",

language = "English",

pages = "681--684",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 IEEE International Electron Devices Meeting, IEDM ; Conference date: 10-12-2007 Through 12-12-2007",

}

Vellianitis, G, Van Dal, MJH, Witters, L, Curatola, G, Doornbos, G, Collaert, N, Jonville, C, Torregiani, C, Lai, LS, Petry, J, Pawlak, BJ, Duffy, R, Demand, M, Beckx, S, Mertens, S, Delabie, A, Vandeweyer, T, Delvaux, C, Leys, F, Hikavyy, A, Rooyackers, R, Kaiser, M, Weemaes, RG, Voogt, F, Roberts, H, Donnet, D, Biesemans, S, Jurczak, M & Lander, RJP 2007, 'Gatestacks for scalable high-performance FinFETs', Technical Digest - International Electron Devices Meeting, pp. 681-684. https://doi.org/10.1109/IEDM.2007.4419037

TY - JOUR

T1 - Gatestacks for scalable high-performance FinFETs

AU - Vellianitis, G.

AU - Van Dal, M. J.H.

AU - Witters, L.

AU - Curatola, G.

AU - Doornbos, G.

AU - Collaert, N.

AU - Jonville, C.

AU - Torregiani, C.

AU - Lai, L. S.

AU - Petry, J.

AU - Pawlak, B. J.

AU - Duffy, R.

AU - Demand, M.

AU - Beckx, S.

AU - Mertens, S.

AU - Delabie, A.

AU - Vandeweyer, T.

AU - Delvaux, C.

AU - Leys, F.

AU - Hikavyy, A.

AU - Rooyackers, R.

AU - Kaiser, M.

AU - Weemaes, R. Gr

AU - Voogt, F.

AU - Roberts, H.

AU - Donnet, D.

AU - Biesemans, S.

AU - Jurczak, M.

AU - Lander, R. J.P.

PY - 2007

Y1 - 2007

N2 - Excellent performance (995μA/μm at Ioff=94nA/μm and Vdd=1V) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193nm immersion lithography and dry etch. PVD TiN electrodes on HfSiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage VT variability is shown to explain this dependence upon fin width and gate length.

AB - Excellent performance (995μA/μm at Ioff=94nA/μm and Vdd=1V) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193nm immersion lithography and dry etch. PVD TiN electrodes on HfSiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage VT variability is shown to explain this dependence upon fin width and gate length.

UR - https://www.scopus.com/pages/publications/50249095101

U2 - 10.1109/IEDM.2007.4419037

DO - 10.1109/IEDM.2007.4419037

M3 - Article

AN - SCOPUS:50249095101

SN - 0163-1918

SP - 681

EP - 684

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

M1 - 4419037

T2 - 2007 IEEE International Electron Devices Meeting, IEDM

Y2 - 10 December 2007 through 12 December 2007

ER -

Gatestacks for scalable high-performance FinFETs

Abstract

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