Ge/Si p-n diode fabricated by direct wafer bonding and layer exfoliation

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

We report on the formation and electrical characterization of current transport across a p-Ge to n-Si diode structure obtained by direct wafer bonding and layer exfoliation. A low temperature anneal at 400°C for 30 minutes improved the forward characteristics of the diode. The Ion/I off ratio > 5 × 104 and > 8 × 10 3 is obtained at -0.5 V and -1 V, respectively. The carrier transport mechanism was analyzed based on the I-V and C-V measurements and direct tunneling is suggested as the transport mechanism. This fabrication technique using a low thermal budget (T ≤ 400°C) is an attractive option for heterogeneous integration.

Original languageEnglish
Title of host publicationSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2
PublisherElectrochemical Society Inc.
Pages131-139
Number of pages9
Edition6
ISBN (Electronic)9781607683162
ISBN (Print)9781566779586
DOIs
Publication statusPublished - 2012
EventInternational Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting - Seattle, WA, United States
Duration: 6 May 201210 May 2012

Publication series

NameECS Transactions
Number6
Volume45
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

ConferenceInternational Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting
Country/TerritoryUnited States
CitySeattle, WA
Period6/05/1210/05/12

Fingerprint

Dive into the research topics of 'Ge/Si p-n diode fabricated by direct wafer bonding and layer exfoliation'. Together they form a unique fingerprint.

Cite this