Hardware implementation of pairings

Maurice Keller; Robert Ronan; Andrew Byrne; Colin Murphy; William Marnane

doi:10.3233/978-1-58603-947-9-207

Hardware implementation of pairings

Maurice Keller
, Robert Ronan
, Andrew Byrne
, Colin Murphy
, William Marnane

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

In this chapter the efficient hardware implementation of pairings is considered. For each of the three fields F_2m, F_3m and F_p suitable curves, pairing algorithms and field arithmetic architectures are presented. An example architecture for computing the η_T pairing in characteristic 2 or 3 is presented and its implementation results on a Xilinx FPGA considered. Finally the implementation results of several pairing architectures from the literature are discussed.

Original language	English
Title of host publication	Identity-Based Cryptography
Publisher	IOS Press
Pages	207-225
Number of pages	19
ISBN (Print)	9781586039479
DOIs	https://doi.org/10.3233/978-1-58603-947-9-207
Publication status	Published - 2009

Publication series

Name	Cryptology and Information Security Series
Volume	2
ISSN (Print)	1871-6431
ISSN (Electronic)	1879-8101

Keywords

BKLS
FPGA
hardware implementation
parallel arithmetic
Tate pairing

Access to Document

10.3233/978-1-58603-947-9-207

Cite this

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AB - In this chapter the efficient hardware implementation of pairings is considered. For each of the three fields F2m, F3m and Fp suitable curves, pairing algorithms and field arithmetic architectures are presented. An example architecture for computing the ηT pairing in characteristic 2 or 3 is presented and its implementation results on a Xilinx FPGA considered. Finally the implementation results of several pairing architectures from the literature are discussed.

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KW - FPGA

KW - hardware implementation

KW - parallel arithmetic

KW - Tate pairing

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M3 - Chapter

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ER -

Hardware implementation of pairings

Abstract

Publication series

Keywords

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