Heterogeneous nano-electronic devices enabled by monolithic integration of IIIV, Ge, and Si to expand future CMOS functionality

Compound-Semiconductor-on-Silicon is a field that has been actively pursued for years with success for mixed-signal applications [1]. This has been in parallel to the aggressive CMOS scaling roadmap. As the demand for higher performance and functionality grows for digital components, to address power and density scaling, the need drives the convergence of new materials and nano-devices. This paper discusses the important aspects of materials, integration, device and circuit implementation of such processes to target 7nm and 5nm CMOS technology nodes. Specifically, defect engineering of III-V and Ge heteroepitaxy in fin replacement process, III-V FinFET device design, Vertical nanowire process and circuits. Since there is no one universal material or device that can address the power and performance need of future electronics, we show that the integration of different device-types will be needed and the method to enable such integration become an important approach.