High aspect ratio junctionless InGaAs FinFETs fabricated using a top-down approach

The junctionless MOSFET (JLFET) architecture has attracted much attention as an enabling technology for ultra-scaled CMOS devices [1]. The dominant scattering mechanism in JLFETs is impurity scattering due to its necessarily highly doped channel [1]. Accordingly, III-V's may offer an even greater advantage as the channel material for JLFETs than for conventional MOSFETs as they suffer less from mobility degradation due to impurity scattering [2]. Current Si CMOS devices employ non-planar architectures with high aspect ratio fins which serve to increase the on current (I_on) per chip surface area [3]. This necessitates that any incarnation of a III - V MOSFET must also exploit the vertical dimension. Additionally, it must do so by employing a 'top-down' fabrication approach to remain compatible with Si CMOS processing. This requires a low D_it dielectric interface to etched III-V fin sidewalls. To date, all III-V junctionless FinFETs (JLFinFETs) demonstrated have employed fin heights which are smaller than the maximum depletion width of their respective channels, and therefore can be well modulated by the top gate only: offering little insight into the effectiveness of the gated sidewalls. We implement a low damage etch process to form high aspect ratio, In₀₅₃Ga₀₄₇As JLFinFETs which have record performance in terms of I_on normalized to fin width.