Hot‐carrier reliability lifetimes as predicted by Berkeley's model

Hot‐carrier effects pose a significant reliability problem in modern MOS processes. An accurate method of predicting hot‐carrier lifetimes is essential for the development of fine‐geometry MOS technology. A hot‐carrier degradation model developed by C. Hu et al. at the University of Berkeley is widely used to predict device lifetimes at given operating conditions from the results of accelerated tests. This paper demonstrates a new method of performing hot‐carrier stress measurements which satisfies the key demand of this model. This method involves adjusting device drain voltage in order to maintain a constant ratio of substrate to drain currents. This method is employed to show that the Berkeley model makes a minimum lifetime prediction which is about an order of magnitude too short at accelerated stress conditions. This casts doubt on the suitability of the Berkeley model for use in circuit reliability simulation and for use in setting industrial reliability benchmarks. A new understanding of the importance of the gate‐source voltage during hot‐carrier reliability characterization using the Berkeley model is also discussed.