TY - CHAP
T1 - Hybrid integration of a CMOS active quench and reset circuit for a geiger-mode avalanche photodiode
AU - Cronin, Donal
AU - Morrison, Alan P.
AU - McCarthy, Kevin G.
PY - 2006
Y1 - 2006
N2 - An active quench and reset circuit (AQRC) is an essential control circuit for ensuring high-speed photon counting with geiger-mode avalanche photodiodes (GMAPs). Its purpose is to turn off the detector when an avalanche has been detected, register a photon count and then reset the device to its quiescent bias voltage after a preset interval, to enable further avalanche events to be counted. This paper presents an AQRC-IC, developed using Europractice's ASIC Service. The purpose of the design was to develop a high-speed CMOS AQRC for hybrid integration with in-house GMAPs. The designed ASIC, developed using AMS' 3.3 V 0.35 μm CMOS process models, includes a ballast resistor for the external GMAP, a comparator sensing-stage, an active quench and an active reset stage. The hold-off time is determined using external silicon delay lines and an FPGA. The ASIC is implemented on a ceramic DIP as is the GMAP, and the AQRC prototype achieves a saturated count-rate of 5 Mcounts/s, an active quench of 45 ns, an active reset of 30 ns and possible increments of the hold-off time between 50 ns and 500 ns.
AB - An active quench and reset circuit (AQRC) is an essential control circuit for ensuring high-speed photon counting with geiger-mode avalanche photodiodes (GMAPs). Its purpose is to turn off the detector when an avalanche has been detected, register a photon count and then reset the device to its quiescent bias voltage after a preset interval, to enable further avalanche events to be counted. This paper presents an AQRC-IC, developed using Europractice's ASIC Service. The purpose of the design was to develop a high-speed CMOS AQRC for hybrid integration with in-house GMAPs. The designed ASIC, developed using AMS' 3.3 V 0.35 μm CMOS process models, includes a ballast resistor for the external GMAP, a comparator sensing-stage, an active quench and an active reset stage. The hold-off time is determined using external silicon delay lines and an FPGA. The ASIC is implemented on a ceramic DIP as is the GMAP, and the AQRC prototype achieves a saturated count-rate of 5 Mcounts/s, an active quench of 45 ns, an active reset of 30 ns and possible increments of the hold-off time between 50 ns and 500 ns.
KW - Active quench and reset circuit (AQRC)
KW - Application Specific Integrated Circuit (ASIC)
KW - Comparator
KW - Field Programmable Gate Array (FPGA)
KW - Geiger-mode avalanche photodiode (GMAP)
KW - Silicon delay line
UR - https://www.scopus.com/pages/publications/33646732166
U2 - 10.1117/12.644108
DO - 10.1117/12.644108
M3 - Chapter
AN - SCOPUS:33646732166
SN - 0819461660
SN - 9780819461667
T3 - Proceedings of SPIE - The International Society for Optical Engineering
BT - Optoelectronic Integrated Circuits VIII
T2 - Optoelectronic Integrated Circuits VIII
Y2 - 23 January 2006 through 25 January 2006
ER -