III-V devices and technology for CMOS

Niamh Waldron

doi:10.1016/B978-0-08-102061-6.00007-0

III-V devices and technology for CMOS

Niamh Waldron

Interuniversitair Micro-Elektronica Centrum

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

In this chapter, advances in the use of III-V materials for both n- and p-MOSFET devices will be reviewed including progress in gate stack technology and its associated reliability. For the full potential of III-V to be realized in advanced CMOS technology nodes, it must be integrated on 300 mm wafers in order to leverage the benefits of the high-volume manufacturing techniques and toolsets used in advanced Si-CMOS manufacturing. Therefore, a strong emphasis in this chapter is placed on how III-V devices may be integrated onto a Si platform in order to be deployed in a manufacturable VLSI-compatible flow.

Original language	English
Title of host publication	High Mobility Materials for CMOS Applications
Publisher	Elsevier
Pages	231-280
Number of pages	50
ISBN (Electronic)	9780081020616
ISBN (Print)	9780081020623
DOIs	https://doi.org/10.1016/B978-0-08-102061-6.00007-0
Publication status	Published - 1 Jan 2018
Externally published	Yes

Keywords

III-V
III-V FinFET
III-V GAA
III-V on Si
III-V-O-I
InAs
InGaAs

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1016/B978-0-08-102061-6.00007-0

Cite this

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title = "III-V devices and technology for CMOS",

abstract = "In this chapter, advances in the use of III-V materials for both n- and p-MOSFET devices will be reviewed including progress in gate stack technology and its associated reliability. For the full potential of III-V to be realized in advanced CMOS technology nodes, it must be integrated on 300 mm wafers in order to leverage the benefits of the high-volume manufacturing techniques and toolsets used in advanced Si-CMOS manufacturing. Therefore, a strong emphasis in this chapter is placed on how III-V devices may be integrated onto a Si platform in order to be deployed in a manufacturable VLSI-compatible flow.",

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AB - In this chapter, advances in the use of III-V materials for both n- and p-MOSFET devices will be reviewed including progress in gate stack technology and its associated reliability. For the full potential of III-V to be realized in advanced CMOS technology nodes, it must be integrated on 300 mm wafers in order to leverage the benefits of the high-volume manufacturing techniques and toolsets used in advanced Si-CMOS manufacturing. Therefore, a strong emphasis in this chapter is placed on how III-V devices may be integrated onto a Si platform in order to be deployed in a manufacturable VLSI-compatible flow.

KW - III-V

KW - III-V FinFET

KW - III-V GAA

KW - III-V on Si

KW - III-V-O-I

KW - InAs

KW - InGaAs

UR - https://www.scopus.com/pages/publications/85080820926

U2 - 10.1016/B978-0-08-102061-6.00007-0

DO - 10.1016/B978-0-08-102061-6.00007-0

M3 - Chapter

AN - SCOPUS:85080820926

SN - 9780081020623

SP - 231

EP - 280

BT - High Mobility Materials for CMOS Applications

PB - Elsevier

ER -

III-V devices and technology for CMOS

Abstract

Keywords

UN SDGs

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