TY - CHAP
T1 - Impact of Through Glass Vias Filling on the Performance of Passive Thermal Cooling in Photonic Packages
AU - Gupta, Parnika
AU - Morrissey, Padraic E.
AU - O'Brien, Peter
AU - Kröhnert, Kevin
AU - Wöhrmann, Markus
AU - Schiffer, Michael
AU - Kelb, Christian
AU - Ambrosius, Norbert
AU - Schneider-Ramelow, Martin
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - In this paper, we examine glass as a 2.5D interposer for next generation photonic packaging, where copper vias have been incorporated in the glass to greatly increase its thermal dissipation characteristics. The thermal performance of 110μm thick glass interposers with and without through glass copper vias (20μm diameter and 100μm pitch) as well as silicon interposer have been investigated. A temperature difference of approximately 38°C has been observed in the maximum temperature of the laser die bonded on glass with and without Through Glass Vias (TGVs). These experimental results have been compared with simulation results, which highlights the via filling factor (FF) effect on the thermal dissipation of glass with TGVs. Simulations have been conducted which show the effects of solder thickness, FF, Via Diameter, Via Pitch, glass thickness and via height on the effective thermal conductivity and maximum surface temperature of the laser die. The laser bonded on all three types of 3mm x 3mm interposers (Glass, Glass with TGVs and Silicon) has many factors affecting the heat dissipation such as thickness of gold layer plated on top of copper vias and via shape which have been explored through simulations. The experimental results act as the reference point to propose optimized design parameters. The surface interaction of thin solder preform for packaging laser dies on glass with copper vias has also been demonstrated through an EDX analysis. This analysis offers a design rule set that can then be implemented in the photonic component packaging on glass with TGV substrates.
AB - In this paper, we examine glass as a 2.5D interposer for next generation photonic packaging, where copper vias have been incorporated in the glass to greatly increase its thermal dissipation characteristics. The thermal performance of 110μm thick glass interposers with and without through glass copper vias (20μm diameter and 100μm pitch) as well as silicon interposer have been investigated. A temperature difference of approximately 38°C has been observed in the maximum temperature of the laser die bonded on glass with and without Through Glass Vias (TGVs). These experimental results have been compared with simulation results, which highlights the via filling factor (FF) effect on the thermal dissipation of glass with TGVs. Simulations have been conducted which show the effects of solder thickness, FF, Via Diameter, Via Pitch, glass thickness and via height on the effective thermal conductivity and maximum surface temperature of the laser die. The laser bonded on all three types of 3mm x 3mm interposers (Glass, Glass with TGVs and Silicon) has many factors affecting the heat dissipation such as thickness of gold layer plated on top of copper vias and via shape which have been explored through simulations. The experimental results act as the reference point to propose optimized design parameters. The surface interaction of thin solder preform for packaging laser dies on glass with copper vias has also been demonstrated through an EDX analysis. This analysis offers a design rule set that can then be implemented in the photonic component packaging on glass with TGV substrates.
KW - Interposer
KW - photonic packaging
KW - Through Glass Vias
UR - https://www.scopus.com/pages/publications/85143162600
U2 - 10.1109/ESTC55720.2022.9939531
DO - 10.1109/ESTC55720.2022.9939531
M3 - Chapter
AN - SCOPUS:85143162600
T3 - 2022 IEEE 9th Electronics System-Integration Technology Conference, ESTC 2022 - Proceedings
SP - 391
EP - 397
BT - 2022 IEEE 9th Electronics System-Integration Technology Conference, ESTC 2022 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th IEEE Electronics System-Integration Technology Conference, ESTC 2022
Y2 - 13 September 2022 through 16 September 2022
ER -