Implementation-Aware Latency and Energy Modeling for Tiling on the Edge

Tiling improves small-object detection on resource-constrained edge devices but can increase latency and energy. This work presents an implementation-aware latency/energy model by decomposing the tiling methodology into per-frame and per-tile events and measuring on-device baselines. It also introduces a relative-object-size–guided anchor-scaling method that derives anchors for arbitrary tiling configurations from a single set via a closed-form scale factor. On the ADI MAX78002 with two RetinaNet Feature Pyramid Network custom variants, model predictions closely match measurements (≈ 2.5 % to 6 % latency error; ≈ 3.4 % to 4.3 % energy error), and scaled anchors match re-computed anchors across tested object detection datasets (SFCHDs and CARPK). Finally, this work provides a practical workflow to pre-filter feasible tiling configurations under latency/energy budgets prior to training and evaluation.