Improved modelling and parameter extraction for parasitic BJT devices in CMOS

Parasitic BJT devices within advanced CMOS processes are regularly used by the circuit designer for increased circuit flexibility. But these devices have less ideal characteristics than those found in bipolar-only processes and present a challenge for characterisation and parameter extraction. In this paper, the problem of providing accurate SPICE models for such parasitic devices is addressed. The results used are of a device from a 0.7 μm process. However, an obstacle to the determination of Gummel-Poon parameters is the strong correlation between some effects. This paper presents a strategy that enables a full set of DC parameters to be extracted for the Gummel-Poon model in a sequence of steps that operate on well-defined subsets of the data at one time and that reduces the use of optimisation and preserves the physical nature of the parameters.